>>> yosys: Building testing/yosys 0.66-r0 (using abuild 3.18.0_rc3-r1) started Wed, 15 Jul 2026 03:20:10 +0000 >>> yosys: Validating /home/buildozer/aports/testing/yosys/APKBUILD... >>> yosys: Analyzing dependencies... >>> yosys: Installing for build: build-base abc bash bison boost-dev flex-dev gawk graphviz-dev libffi-dev lld protobuf-dev py3-cxxheaderparser py3-pybind11-dev python3 readline-dev tcl-dev zlib-dev gtest-dev gtkwave iverilog ( 1/365) Installing readline (8.3.3-r1) Installing file to etc/inputrc.apk-new ( 2/365) Installing abc (0_git20260515-r0) ( 3/365) Installing bash (5.3.9-r1) Executing bash-5.3.9-r1.post-install ( 4/365) Installing m4 (1.4.21-r0) ( 5/365) Installing bison (3.8.2-r3) ( 6/365) Installing boost1.84-atomic (1.84.0-r6) ( 7/365) Installing boost1.84-chrono (1.84.0-r6) ( 8/365) Installing boost1.84-container (1.84.0-r6) ( 9/365) Installing boost1.84-context (1.84.0-r6) ( 10/365) Installing boost1.84-contract (1.84.0-r6) ( 11/365) Installing boost1.84-coroutine (1.84.0-r6) ( 12/365) Installing boost1.84-date_time (1.84.0-r6) ( 13/365) Installing boost1.84-fiber (1.84.0-r6) ( 14/365) Installing boost1.84-filesystem (1.84.0-r6) ( 15/365) Installing boost1.84-graph (1.84.0-r6) ( 16/365) Installing libbz2 (1.0.8-r6) ( 17/365) Installing xz-libs (5.8.3-r0) ( 18/365) Installing boost1.84-iostreams (1.84.0-r6) ( 19/365) Installing boost1.84-thread (1.84.0-r6) ( 20/365) Installing icu-data-en (78.1-r0) Executing icu-data-en-78.1-r0.post-install * If you need ICU with non-English locales and legacy charset support, install * package icu-data-full. ( 21/365) Installing icu-libs (78.1-r0) ( 22/365) Installing boost1.84-locale (1.84.0-r6) ( 23/365) Installing boost1.84-log (1.84.0-r6) ( 24/365) Installing boost1.84-log_setup (1.84.0-r6) ( 25/365) Installing boost1.84-math (1.84.0-r6) ( 26/365) Installing boost1.84-prg_exec_monitor (1.84.0-r6) ( 27/365) Installing boost1.84-program_options (1.84.0-r6) ( 28/365) Installing libffi (3.5.2-r1) ( 29/365) Installing mpdecimal (4.0.1-r0) ( 30/365) Installing libpanelw (6.6_p20260516-r0) ( 31/365) Installing sqlite-libs (3.53.3-r0) ( 32/365) Installing python3 (3.14.5-r2) ( 33/365) Installing python3-pycache-pyc0 (3.14.5-r2) ( 34/365) Installing pyc (3.14.5-r2) ( 35/365) Installing python3-pyc (3.14.5-r2) ( 36/365) Installing boost1.84-python3 (1.84.0-r6) ( 37/365) Installing boost1.84-random (1.84.0-r6) ( 38/365) Installing boost1.84-regex (1.84.0-r6) ( 39/365) Installing boost1.84-serialization (1.84.0-r6) ( 40/365) Installing boost1.84-stacktrace_basic (1.84.0-r6) ( 41/365) Installing boost1.84-stacktrace_noop (1.84.0-r6) ( 42/365) Installing boost1.84-system (1.84.0-r6) ( 43/365) Installing boost1.84-timer (1.84.0-r6) ( 44/365) Installing boost1.84-type_erasure (1.84.0-r6) ( 45/365) Installing boost1.84-unit_test_framework (1.84.0-r6) ( 46/365) Installing boost1.84-url (1.84.0-r6) ( 47/365) Installing boost1.84-wave (1.84.0-r6) ( 48/365) Installing boost1.84-wserialization (1.84.0-r6) ( 49/365) Installing boost1.84-json (1.84.0-r6) ( 50/365) Installing boost1.84-nowide (1.84.0-r6) ( 51/365) Installing boost1.84-libs (1.84.0-r6) ( 52/365) Installing boost1.84 (1.84.0-r6) ( 53/365) Installing linux-headers (7.1.3-r0) ( 54/365) Installing bzip2-dev (1.0.8-r6) ( 55/365) Installing icu (78.1-r0) ( 56/365) Installing icu-dev (78.1-r0) ( 57/365) Installing xz (5.8.3-r0) ( 58/365) Installing xz-dev (5.8.3-r0) ( 59/365) Installing zlib-dev (1.3.2-r0) ( 60/365) Installing zstd (1.5.7-r2) ( 61/365) Installing zstd-dev (1.5.7-r2) ( 62/365) Installing boost1.84-dev (1.84.0-r6) ( 63/365) Installing boost-dev (1.84.0-r6) ( 64/365) Installing flex (2.6.4-r8) ( 65/365) Installing flex-libs (2.6.4-r8) ( 66/365) Installing flex-dev (2.6.4-r8) ( 67/365) Installing gawk (5.3.2-r2) ( 68/365) Installing cairo-tools (1.18.4-r1) ( 69/365) Installing libxau (1.0.12-r0) ( 70/365) Installing libmd (1.2.0-r0) ( 71/365) Installing libbsd (0.12.2-r0) ( 72/365) Installing libxdmcp (1.1.5-r1) ( 73/365) Installing libxcb (1.17.0-r2) ( 74/365) Installing libx11 (1.8.13-r0) ( 75/365) Installing libxext (1.3.7-r0) ( 76/365) Installing libxrender (0.9.12-r0) ( 77/365) Installing libpng (1.6.58-r1) ( 78/365) Installing freetype (2.14.3-r0) ( 79/365) Installing fontconfig (2.18.1-r0) ( 80/365) Installing pixman (0.46.4-r0) ( 81/365) Installing cairo (1.18.4-r1) ( 82/365) Installing libeconf (0.8.3-r0) ( 83/365) Installing libblkid (2.42.2-r0) ( 84/365) Installing libmount (2.42.2-r0) ( 85/365) Installing glib (2.88.2-r0) ( 86/365) Installing cairo-gobject (1.18.4-r1) ( 87/365) Installing expat (2.8.2-r0) ( 88/365) Installing expat-dev (2.8.2-r0) ( 89/365) Installing brotli (1.2.0-r1) ( 90/365) Installing brotli-dev (1.2.0-r1) ( 91/365) Installing libpng-dev (1.6.58-r1) ( 92/365) Installing freetype-dev (2.14.3-r0) ( 93/365) Installing fontconfig-dev (2.18.1-r0) ( 94/365) Installing libxml2 (2.13.9-r2) ( 95/365) Installing libxml2-utils (2.13.9-r2) ( 96/365) Installing docbook-xml (4.5-r10) Executing docbook-xml-4.5-r10.post-install ( 97/365) Installing libxslt (1.1.43-r3) ( 98/365) Installing docbook-xsl-ns (1.79.2-r13) Executing docbook-xsl-ns-1.79.2-r13.post-install ( 99/365) Installing docbook-xsl-nons (1.79.2-r13) Executing docbook-xsl-nons-1.79.2-r13.post-install (100/365) Installing docbook-xsl (1.79.2-r13) (101/365) Installing gettext-asprintf (1.0-r0) (102/365) Installing gettext-libs (1.0-r0) (103/365) Installing gettext (1.0-r0) (104/365) Installing gettext-dev (1.0-r0) (105/365) Installing py3-parsing (3.3.2-r1) (106/365) Installing py3-parsing-pyc (3.3.2-r1) (107/365) Installing py3-packaging (26.2-r0) (108/365) Installing py3-packaging-pyc (26.2-r0) (109/365) Installing libffi-dev (3.5.2-r1) (110/365) Installing bsd-compat-headers (0.7.2-r6) (111/365) Installing libformw (6.6_p20260516-r0) (112/365) Installing libmenuw (6.6_p20260516-r0) (113/365) Installing libncurses++ (6.6_p20260516-r0) (114/365) Installing ncurses-dev (6.6_p20260516-r0) (115/365) Installing libedit-dev (20260508.3.1-r1) (116/365) Installing libpcre2-16 (10.47-r1) (117/365) Installing libpcre2-32 (10.47-r1) (118/365) Installing pcre2-dev (10.47-r1) (119/365) Installing libuuid (2.42.2-r0) (120/365) Installing libfdisk (2.42.2-r0) (121/365) Installing skalibs-libs (2.15.1.0-r0) (122/365) Installing utmps-libs (0.1.3.4-r0) (123/365) Installing linux-pam (1.7.1-r2) Installing file to etc/environment.apk-new Installing file to etc/security/access.conf.apk-new Installing file to etc/security/faillock.conf.apk-new Installing file to etc/security/group.conf.apk-new Installing file to etc/security/limits.conf.apk-new Installing file to etc/security/namespace.conf.apk-new Installing file to etc/security/namespace.init.apk-new Installing file to etc/security/pam_env.conf.apk-new Installing file to etc/security/pwhistory.conf.apk-new Installing file to etc/security/time.conf.apk-new (124/365) Installing liblastlog2 (2.42.2-r0) (125/365) Installing libsmartcols (2.42.2-r0) (126/365) Installing sqlite (3.53.3-r0) (127/365) Installing sqlite-dev (3.53.3-r0) (128/365) Installing util-linux-dev (2.42.2-r0) (129/365) Installing glib-dev (2.88.2-r0) (130/365) Installing pixman-dev (0.46.4-r0) (131/365) Installing xorgproto (2025.1-r0) (132/365) Installing libxau-dev (1.0.12-r0) (133/365) Installing xcb-proto (1.17.0-r1) (134/365) Installing xcb-proto-pyc (1.17.0-r1) (135/365) Installing libxdmcp-dev (1.1.5-r1) (136/365) Installing libxcb-dev (1.17.0-r2) (137/365) Installing xtrans (1.6.0-r0) (138/365) Installing libx11-dev (1.8.13-r0) (139/365) Installing libxext-dev (1.3.7-r0) (140/365) Installing libxrender-dev (0.9.12-r0) (141/365) Installing cairo-dev (1.18.4-r1) (142/365) Installing libice (1.1.2-r0) (143/365) Installing libsm (1.2.6-r0) (144/365) Installing libxt (1.3.1-r0) (145/365) Installing libxpm (3.5.19-r0) (146/365) Installing aom-libs (3.14.1-r0) (147/365) Installing libdav1d (1.5.3-r0) (148/365) Installing libjpeg-turbo (3.1.3-r0) (149/365) Installing libyuv (0.0.1928-r0) (150/365) Installing libavif (1.4.2-r0) (151/365) Installing libsharpyuv (1.6.0-r0) (152/365) Installing libwebp (1.6.0-r0) (153/365) Installing tiff (4.7.1-r0) (154/365) Installing libgd (2.3.3-r10) (155/365) Installing gd (2.3.3-r10) (156/365) Installing perl (5.42.2-r0) (157/365) Installing aom (3.14.1-r0) (158/365) Installing aom-dev (3.14.1-r0) (159/365) Installing dav1d-dev (1.5.3-r0) (160/365) Installing libavif-dev (1.4.2-r0) (161/365) Installing libturbojpeg (3.1.3-r0) (162/365) Installing libjpeg-turbo-dev (3.1.3-r0) (163/365) Installing libtiffxx (4.7.1-r0) (164/365) Installing libwebpdecoder (1.6.0-r0) (165/365) Installing libwebpdemux (1.6.0-r0) (166/365) Installing libwebpmux (1.6.0-r0) (167/365) Installing libwebp-dev (1.6.0-r0) (168/365) Installing tiff-dev (4.7.1-r0) (169/365) Installing libxpm-dev (3.5.19-r0) (170/365) Installing gd-dev (2.3.3-r10) (171/365) Installing libgmpxx (6.3.0-r4) (172/365) Installing gmp-dev (6.3.0-r4) (173/365) Installing libice-dev (1.1.2-r0) (174/365) Installing libsm-dev (1.2.6-r0) (175/365) Installing libxft (2.3.9-r0) (176/365) Installing graphite2 (1.3.15-r0) (177/365) Installing harfbuzz (14.2.1-r0) (178/365) Installing fribidi (1.0.16-r3) (179/365) Installing pango (1.57.1-r0) (180/365) Installing pango-tools (1.57.1-r0) (181/365) Installing fribidi-dev (1.0.16-r3) (182/365) Installing harfbuzz-cairo (14.2.1-r0) (183/365) Installing harfbuzz-gobject (14.2.1-r0) (184/365) Installing harfbuzz-icu (14.2.1-r0) (185/365) Installing harfbuzz-subset (14.2.1-r0) (186/365) Installing graphite2-dev (1.3.15-r0) (187/365) Installing harfbuzz-dev (14.2.1-r0) (188/365) Installing libxft-dev (2.3.9-r0) (189/365) Installing pango-dev (1.57.1-r0) (190/365) Installing python3-dev (3.14.5-r2) (191/365) Installing graphviz-libs (12.2.1-r3) (192/365) Installing graphviz-dev (12.2.1-r3) (193/365) Installing llvm22-libs (22.1.8-r0) (194/365) Installing lld22-libs (22.1.8-r0) (195/365) Installing scudo-malloc (22.1.8-r0) (196/365) Installing lld22 (22.1.8-r0) (197/365) Installing abseil-cpp-raw-logging-internal (20260526.0-r0) (198/365) Installing abseil-cpp-spinlock-wait (20260526.0-r0) (199/365) Installing abseil-cpp-base (20260526.0-r0) (200/365) Installing abseil-cpp-city (20260526.0-r0) (201/365) Installing abseil-cpp-civil-time (20260526.0-r0) (202/365) Installing abseil-cpp-strings-internal (20260526.0-r0) (203/365) Installing abseil-cpp-throw-delegate (20260526.0-r0) (204/365) Installing abseil-cpp-strings (20260526.0-r0) (205/365) Installing abseil-cpp-time-zone (20260526.0-r0) (206/365) Installing abseil-cpp-time (20260526.0-r0) (207/365) Installing abseil-cpp-kernel-timeout-internal (20260526.0-r0) (208/365) Installing abseil-cpp-malloc-internal (20260526.0-r0) (209/365) Installing abseil-cpp-debugging-internal (20260526.0-r0) (210/365) Installing abseil-cpp-stacktrace (20260526.0-r0) (211/365) Installing abseil-cpp-tracing-internal (20260526.0-r0) (212/365) Installing abseil-cpp-synchronization (20260526.0-r0) (213/365) Installing abseil-cpp-clock-interface (20260526.0-r0) (214/365) Installing abseil-cpp-crc-internal (20260526.0-r0) (215/365) Installing abseil-cpp-crc32c (20260526.0-r0) (216/365) Installing abseil-cpp-crc-cord-state (20260526.0-r0) (217/365) Installing abseil-cpp-cord-internal (20260526.0-r0) (218/365) Installing abseil-cpp-exponential-biased (20260526.0-r0) (219/365) Installing abseil-cpp-cordz-functions (20260526.0-r0) (220/365) Installing abseil-cpp-cordz-handle (20260526.0-r0) (221/365) Installing abseil-cpp-cordz-info (20260526.0-r0) (222/365) Installing abseil-cpp-cord (20260526.0-r0) (223/365) Installing abseil-cpp-cordz-sample-token (20260526.0-r0) (224/365) Installing abseil-cpp-crc-cpu-detect (20260526.0-r0) (225/365) Installing abseil-cpp-utf8-for-code-point (20260526.0-r0) (226/365) Installing abseil-cpp-decode-rust-punycode (20260526.0-r0) (227/365) Installing abseil-cpp-demangle-rust (20260526.0-r0) (228/365) Installing abseil-cpp-demangle-internal (20260526.0-r0) (229/365) Installing abseil-cpp-symbolize (20260526.0-r0) (230/365) Installing abseil-cpp-examine-stack (20260526.0-r0) (231/365) Installing abseil-cpp-hash (20260526.0-r0) (232/365) Installing abseil-cpp-log-globals (20260526.0-r0) (233/365) Installing abseil-cpp-log-internal-globals (20260526.0-r0) (234/365) Installing abseil-cpp-int128 (20260526.0-r0) (235/365) Installing abseil-cpp-str-format-internal (20260526.0-r0) (236/365) Installing abseil-cpp-log-internal-format (20260526.0-r0) (237/365) Installing abseil-cpp-log-sink (20260526.0-r0) (238/365) Installing abseil-cpp-log-internal-log-sink-set (20260526.0-r0) (239/365) Installing abseil-cpp-log-internal-nullguard (20260526.0-r0) (240/365) Installing abseil-cpp-log-internal-proto (20260526.0-r0) (241/365) Installing abseil-cpp-log-internal-structured-proto (20260526.0-r0) (242/365) Installing abseil-cpp-strerror (20260526.0-r0) (243/365) Installing abseil-cpp-log-internal-message (20260526.0-r0) (244/365) Installing abseil-cpp-die-if-null (20260526.0-r0) (245/365) Installing gtest (1.17.0-r1) (246/365) Installing abseil-cpp-exception-safety-testing (20260526.0-r0) (247/365) Installing abseil-cpp-failure-signal-handler (20260526.0-r0) (248/365) Installing abseil-cpp-flags-commandlineflag-internal (20260526.0-r0) (249/365) Installing abseil-cpp-flags-commandlineflag (20260526.0-r0) (250/365) Installing abseil-cpp-flags-program-name (20260526.0-r0) (251/365) Installing abseil-cpp-flags-config (20260526.0-r0) (252/365) Installing abseil-cpp-flags-internal (20260526.0-r0) (253/365) Installing abseil-cpp-flags-marshalling (20260526.0-r0) (254/365) Installing abseil-cpp-flags-private-handle-accessor (20260526.0-r0) (255/365) Installing abseil-cpp-hashtablez-sampler (20260526.0-r0) (256/365) Installing abseil-cpp-raw-hash-set (20260526.0-r0) (257/365) Installing abseil-cpp-flags-reflection (20260526.0-r0) (258/365) Installing abseil-cpp-flags-usage (20260526.0-r0) (259/365) Installing abseil-cpp-flags-usage-internal (20260526.0-r0) (260/365) Installing abseil-cpp-flags-parse (20260526.0-r0) (261/365) Installing abseil-cpp-generic-printer-internal (20260526.0-r0) (262/365) Installing abseil-cpp-graphcycles-internal (20260526.0-r0) (263/365) Installing abseil-cpp-random-internal-randen-hwaes (20260526.0-r0) (264/365) Installing abseil-cpp-random-internal-randen-hwaes-impl (20260526.0-r0) (265/365) Installing abseil-cpp-random-internal-platform (20260526.0-r0) (266/365) Installing abseil-cpp-random-internal-randen-slow (20260526.0-r0) (267/365) Installing abseil-cpp-random-internal-randen (20260526.0-r0) (268/365) Installing abseil-cpp-random-internal-seed-material (20260526.0-r0) (269/365) Installing abseil-cpp-random-seed-gen-exception (20260526.0-r0) (270/365) Installing abseil-cpp-random-internal-entropy-pool (20260526.0-r0) (271/365) Installing abseil-cpp-hash-generator-testing (20260526.0-r0) (272/365) Installing abseil-cpp-profile-builder (20260526.0-r0) (273/365) Installing abseil-cpp-hashtable-profiler (20260526.0-r0) (274/365) Installing abseil-cpp-leak-check (20260526.0-r0) (275/365) Installing abseil-cpp-log-severity (20260526.0-r0) (276/365) Installing abseil-cpp-log-entry (20260526.0-r0) (277/365) Installing abseil-cpp-log-internal-fnmatch (20260526.0-r0) (278/365) Installing abseil-cpp-vlog-config-internal (20260526.0-r0) (279/365) Installing abseil-cpp-log-flags (20260526.0-r0) (280/365) Installing abseil-cpp-log-initialize (20260526.0-r0) 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(20260526.0-r0) (296/365) Installing abseil-cpp-simulated-clock (20260526.0-r0) (297/365) Installing abseil-cpp-source-location (20260526.0-r0) (298/365) Installing abseil-cpp-spinlock-test-common (20260526.0-r0) (299/365) Installing abseil-cpp-stack-consumption (20260526.0-r0) (300/365) Installing abseil-cpp-status (20260526.0-r0) (301/365) Installing abseil-cpp-status-builder (20260526.0-r0) (302/365) Installing abseil-cpp-status-matchers (20260526.0-r0) (303/365) Installing abseil-cpp-statusor (20260526.0-r0) (304/365) Installing abseil-cpp-test-instance-tracker (20260526.0-r0) (305/365) Installing abseil-cpp-time-internal-test-util (20260526.0-r0) (306/365) Installing abseil-cpp-dev (20260526.0-r0) (307/365) Installing libprotobuf-lite (31.1-r2) (308/365) Installing protobuf (31.1-r2) (309/365) Installing libprotobuf (31.1-r2) (310/365) Installing libprotoc (31.1-r2) (311/365) Installing protoc (31.1-r2) (312/365) Installing protobuf-dev (31.1-r2) (313/365) Installing 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by default. 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>>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.66.tar.gz Connecting to distfiles.alpinelinux.org (172.105.82.32:443) wget: server returned error: HTTP/1.1 404 Not Found >>> yosys: Fetching yosys-0.66.tar.gz::https://github.com/YosysHQ/yosys/releases/download/v0.66/yosys-src.tar.gz Connecting to github.com (140.82.121.3:443) Connecting to release-assets.githubusercontent.com (185.199.111.133:443) saving to '/var/cache/distfiles/edge/yosys-0.66.tar.gz.part' yosys-0.66.tar.gz.pa 100% |********************************| 10.6M 0:00:00 ETA '/var/cache/distfiles/edge/yosys-0.66.tar.gz.part' saved /var/cache/distfiles/edge/yosys-0.66.tar.gz: OK /home/buildozer/aports/testing/yosys/fix-32-bit-oom.patch: OK /home/buildozer/aports/testing/yosys/fix-libyosys-python-link.patch: OK /home/buildozer/aports/testing/yosys/fix-pybind11-unused-parameter.patch: OK >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.66.tar.gz /var/cache/distfiles/edge/yosys-0.66.tar.gz: OK /home/buildozer/aports/testing/yosys/fix-32-bit-oom.patch: OK /home/buildozer/aports/testing/yosys/fix-libyosys-python-link.patch: OK /home/buildozer/aports/testing/yosys/fix-pybind11-unused-parameter.patch: OK >>> yosys: Unpacking /var/cache/distfiles/edge/yosys-0.66.tar.gz... >>> yosys: fix-32-bit-oom.patch patching file Makefile Hunk #1 succeeded at 789 (offset 7 lines). >>> yosys: fix-libyosys-python-link.patch patching file Makefile Hunk #1 succeeded at 781 (offset 3 lines). >>> yosys: fix-pybind11-unused-parameter.patch patching file kernel/yosys.cc patching file pyosys/hashlib.h [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 [ 0%] Building kernel/version_7f8fdfd8d7bc08c749a2a969388d3425d4f369d5.cc [ 0%] Building pyosys/wrappers.cc [ 0%] Building kernel/driver.o [ 0%] Building techlibs/common/simlib_help.inc [ 0%] Building techlibs/common/simcells_help.inc [ 1%] Building kernel/rtlil.o [ 1%] Building kernel/log.o [ 1%] Building kernel/calc.o [ 2%] Building kernel/yosys.o [ 2%] Building kernel/io.o [ 2%] Building kernel/gzip.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/binding.h [ 2%] Building kernel/rtlil_bufnorm.o [ 3%] Building kernel/log_help.o [ 3%] Building kernel/binding.o [ 3%] Building kernel/tclapi.o [ 3%] Building kernel/cellaigs.o [ 4%] Building kernel/celledges.o [ 4%] Building kernel/cost.o [ 4%] Building kernel/satgen.o [ 4%] Building kernel/scopeinfo.o [ 5%] Building kernel/qcsat.o [ 5%] Building kernel/mem.o [ 5%] Building kernel/ffmerge.o [ 6%] Building kernel/ff.o [ 6%] Building kernel/yw.o [ 6%] Building kernel/json.o [ 6%] Building kernel/fmt.o [ 7%] Building kernel/sexpr.o [ 7%] Building kernel/drivertools.o [ 7%] Building kernel/functional.o [ 7%] Building kernel/threading.o [ 8%] Building kernel/fstdata.o [ 8%] Building libs/bigint/BigIntegerAlgorithms.o [ 8%] Building libs/bigint/BigInteger.o [ 8%] Building libs/bigint/BigIntegerUtils.o [ 9%] Building libs/bigint/BigUnsigned.o [ 9%] Building libs/bigint/BigUnsignedInABase.o [ 9%] Building libs/sha1/sha1.o [ 9%] Building libs/json11/json11.o [ 10%] Building libs/ezsat/ezsat.o [ 10%] Building libs/ezsat/ezminisat.o [ 10%] Building libs/ezsat/ezcmdline.o [ 11%] Building libs/minisat/Options.o [ 11%] Building libs/minisat/SimpSolver.o [ 11%] Building libs/minisat/Solver.o [ 11%] Building libs/minisat/System.o [ 12%] Building libs/fst/fstapi.o [ 12%] Building libs/fst/fastlz.o [ 12%] Building libs/fst/lz4.o [ 12%] Building libs/subcircuit/subcircuit.o [ 13%] Building frontends/aiger/aigerparse.o [ 13%] Building frontends/aiger2/xaiger.o [ 13%] Building frontends/ast/ast.o [ 13%] Building frontends/ast/simplify.o [ 14%] Building frontends/ast/genrtlil.o [ 14%] Building frontends/ast/dpicall.o [ 14%] Building frontends/ast/ast_binding.o [ 14%] Building frontends/blif/blifparse.o [ 15%] Building frontends/json/jsonparse.o [ 15%] Building frontends/liberty/liberty.o [ 15%] Building frontends/rpc/rpc_frontend.o [ 16%] Building frontends/rtlil/rtlil_frontend.o [ 16%] Building frontends/verific/verific.o [ 16%] Building frontends/verilog/verilog_parser.tab.cc [ 17%] Building frontends/verilog/verilog_error.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/libs/sha1/sha1.h [ 17%] Building frontends/verilog/const2ast.o [ 18%] Building passes/cmds/exec.o [ 18%] Building passes/cmds/add.o [ 18%] Building passes/cmds/delete.o [ 18%] Building passes/cmds/design.o [ 19%] Building passes/cmds/design_equal.o In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/SimpSolver.cc:92:26: required from here 92 | occurs .init (v); | ~~~~~~~~~~~~~~~~~^~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 19%] Building passes/cmds/select.o [ 19%] Building passes/cmds/show.o [ 19%] Building passes/cmds/viz.o [ 20%] Building passes/cmds/rename.o [ 20%] Building passes/cmds/autoname.o [ 20%] Building passes/cmds/connect.o [ 20%] Building passes/cmds/scatter.o [ 21%] Building passes/cmds/setundef.o [ 21%] Building passes/cmds/splitnets.o [ 21%] Building passes/cmds/splitcells.o [ 22%] Building passes/cmds/stat.o [ 22%] Building passes/cmds/internal_stats.o [ 22%] Building passes/cmds/setattr.o [ 22%] Building passes/cmds/copy.o [ 23%] Building passes/cmds/splice.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/log.h In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/Solver.cc:134:19: required from here 134 | watches .init(mkLit(v, false)); | ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 23%] Building passes/cmds/scc.o [ 23%] Building passes/cmds/glift.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/yosys.h [ 23%] Building passes/cmds/torder.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/cost.h [ 24%] Building passes/cmds/logcmd.o [ 24%] Building passes/cmds/tee.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/celltypes.h [ 24%] Building passes/cmds/write_file.o [ 24%] Building passes/cmds/connwrappers.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/consteval.h [ 25%] Building passes/cmds/trace.o [ 25%] Building passes/cmds/plugin.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/register.h [ 25%] Building passes/cmds/edgetypes.o [ 25%] Building passes/cmds/check.o + g++ -fsyntax-only -std=c++20 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/rtlil.h [ 26%] Building passes/cmds/portlist.o [ 26%] Building passes/cmds/chformal.o [ 26%] Building passes/cmds/chtype.o [ 27%] Building passes/cmds/blackbox.o [ 27%] Building passes/cmds/ltp.o [ 27%] Building passes/cmds/linux_perf.o [ 27%] Building passes/cmds/bugpoint.o [ 28%] Building passes/cmds/scratchpad.o [ 28%] Building passes/cmds/logger.o [ 28%] Building passes/cmds/printattrs.o [ 28%] Building passes/cmds/sta.o [ 29%] Building passes/cmds/clean_zerowidth.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from ./kernel/cost.h:23, from kernel/cost.cc:1: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from kernel/cost.cc:2: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 29%] Building passes/cmds/xprop.o [ 29%] Building passes/cmds/dft_tag.o [ 29%] Building passes/cmds/future.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from frontends/aiger2/xaiger.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 30%] Building passes/cmds/box_derive.o kernel/drivertools.cc: In member function 'bool Yosys::DriveChunkMultiple::try_append(const Yosys::DriveBitMultiple&)': kernel/drivertools.cc:263:79: warning: 'constant' may be used uninitialized [-Wmaybe-uninitialized] 263 | single.constant().append(RTLIL::Const(constant)); | ^ kernel/drivertools.cc:252:15: note: 'constant' was declared here 252 | State constant; | ^~~~~~~~ [ 30%] Building passes/cmds/example_dt.o [ 30%] Building passes/cmds/portarcs.o [ 30%] Building passes/cmds/wrapcell.o [ 31%] Building passes/cmds/setenv.o [ 31%] Building passes/cmds/abstract.o [ 31%] Building passes/cmds/test_select.o [ 32%] Building passes/cmds/timeest.o [ 32%] Building passes/cmds/linecoverage.o [ 32%] Building passes/cmds/sort.o [ 32%] Building passes/cmds/icell_liberty.o [ 33%] Building passes/cmds/sdc/sdc.o [ 33%] Building passes/equiv/equiv_make.o [ 33%] Building passes/equiv/equiv_miter.o [ 33%] Building passes/equiv/equiv_simple.o [ 34%] Building passes/equiv/equiv_status.o [ 34%] Building passes/equiv/equiv_add.o [ 34%] Building passes/equiv/equiv_remove.o [ 34%] Building passes/equiv/equiv_induct.o [ 35%] Building passes/equiv/equiv_struct.o [ 35%] Building passes/equiv/equiv_purge.o [ 35%] Building passes/equiv/equiv_mark.o [ 35%] Building passes/equiv/equiv_opt.o [ 36%] Building passes/fsm/fsm.o [ 36%] Building passes/fsm/fsm_detect.o [ 36%] Building passes/fsm/fsm_extract.o [ 36%] Building passes/fsm/fsm_opt.o [ 37%] Building passes/fsm/fsm_expand.o [ 37%] Building passes/fsm/fsm_recode.o [ 37%] Building passes/fsm/fsm_info.o [ 38%] Building passes/fsm/fsm_export.o [ 38%] Building passes/fsm/fsm_map.o [ 38%] Building passes/hierarchy/flatten.o In file included from ./kernel/yosys.h:42, from passes/cmds/abstract.cc:1: passes/cmds/abstract.cc: In member function 'virtual void {anonymous}::AbstractPass::execute(std::vector >, Yosys::RTLIL::Design*)': ./kernel/log.h:278:77: warning: this statement may fall through [-Wimplicit-fallthrough=] 278 | # define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__) passes/cmds/abstract.cc:471:41: note: in expansion of macro 'log_assert' 471 | log_assert(false); | ^~~~~~~~~~ passes/cmds/abstract.cc:472:33: note: here 472 | case Enable::ActiveLow: | ^~~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/cmds/scc.cc:24: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::Cell*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::Cell*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 38%] Building passes/hierarchy/hierarchy.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from kernel/rtlil_bufnorm.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:541:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:686:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:541:67: note: '' declared here 541 | entries.emplace_back(std::pair(key, T()), -1); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:541:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:686:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:541:67: note: '' declared here 541 | entries.emplace_back(std::pair(key, T()), -1); | ^~~ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:544:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:686:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:544:67: note: '' declared here 544 | entries.emplace_back(std::pair(key, T()), hashtable[hash]); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:544:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:686:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:544:67: note: '' declared here 544 | entries.emplace_back(std::pair(key, T()), hashtable[hash]); | ^~~ [ 39%] Building passes/hierarchy/uniquify.o [ 39%] Building passes/hierarchy/submod.o [ 39%] Building passes/hierarchy/keep_hierarchy.o [ 39%] Building passes/memory/memory.o [ 40%] Building passes/memory/memory_dff.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23, from ./kernel/satgen.h:23, from kernel/satgen.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/satgen.h:26: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 40%] Building passes/memory/memory_share.o [ 40%] Building passes/memory/memory_collect.o [ 40%] Building passes/memory/memory_unpack.o [ 41%] Building passes/memory/memory_bram.o [ 41%] Building passes/memory/memory_map.o [ 41%] Building passes/memory/memory_memx.o [ 41%] Building passes/memory/memory_nordff.o [ 42%] Building passes/memory/memory_narrow.o [ 42%] Building passes/memory/memory_libmap.o [ 42%] Building passes/memory/memory_bmux2rom.o [ 43%] Building passes/memory/memlib.o [ 43%] Building passes/opt/opt.o [ 43%] Building passes/opt/opt_merge.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/cmds/wrapcell.cc:19: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 43%] Building passes/opt/opt_mem.o [ 44%] Building passes/opt/opt_mem_feedback.o [ 44%] Building passes/opt/opt_mem_priority.o [ 44%] Building passes/opt/opt_mem_widen.o [ 44%] Building passes/opt/opt_muxtree.o [ 45%] Building passes/opt/opt_reduce.o [ 45%] Building passes/opt/opt_dff.o [ 45%] Building passes/opt/opt_share.o [ 45%] Building passes/opt/opt_expr.o [ 46%] Building passes/opt/opt_hier.o [ 46%] Building passes/opt/share.o [ 46%] Building passes/opt/wreduce.o [ 46%] Building passes/opt/opt_demorgan.o [ 47%] Building passes/opt/rmports.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from passes/fsm/fsm_opt.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:475: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 47%] Building passes/opt/opt_lut.o [ 47%] Building passes/opt/opt_lut_ins.o [ 48%] Building passes/opt/opt_ffinv.o passes/opt/opt_merge.cc: In member function '{anonymous}::FoundDuplicates {anonymous}::OptMergeThreadWorker::find_duplicate_cells(int, const {anonymous}::Shards&) const': passes/opt/opt_merge.cc:330:65: warning: redundant move in initialization [-Wredundant-move] 330 | std::vector bucket = std::move(buckets[index]); | ~~~~~~~~~^~~~~~~~~~~~~~~~ passes/opt/opt_merge.cc:330:65: note: remove 'std::move' call [ 48%] Building passes/opt/pmux2shiftx.o [ 48%] Building passes/opt/muxpack.o [ 48%] Building passes/opt/opt_balance_tree.o [ 48%] Building passes/opt/peepopt_pm.h [ 49%] Building passes/opt/opt_clean/cells_all.o [ 49%] Building passes/opt/opt_clean/cells_temp.o [ 49%] Building passes/opt/opt_clean/wires.o [ 50%] Building passes/opt/opt_clean/inits.o [ 50%] Building passes/opt/opt_clean/opt_clean.o [ 50%] Building passes/pmgen/test_pmgen_pm.h [ 50%] Building techlibs/ice40/ice40_dsp_pm.h [ 50%] Building techlibs/xilinx/xilinx_srl_pm.h [ 50%] Building passes/proc/proc.o [ 51%] Building passes/proc/proc_prune.o [ 51%] Building passes/proc/proc_clean.o [ 51%] Building passes/proc/proc_rmdead.o [ 51%] Building passes/proc/proc_init.o [ 52%] Building passes/proc/proc_arst.o [ 52%] Building passes/proc/proc_rom.o [ 52%] Building passes/proc/proc_mux.o [ 53%] Building passes/proc/proc_dlatch.o [ 53%] Building passes/proc/proc_dff.o [ 53%] Building passes/proc/proc_memwr.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from ./kernel/celltypes.h:23, from passes/cmds/dft_tag.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const std::pair&; _U2 = Yosys::RTLIL::SigSpec; _T1 = std::pair; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = std::pair; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::DftTagWorker::divert_users(Yosys::RTLIL::SigBit, Yosys::RTLIL::SigBit)' at passes/cmds/dft_tag.cc:149:21, inlined from 'Yosys::RTLIL::SigSpec {anonymous}::DftTagWorker::divert_users(Yosys::RTLIL::SigSpec)' at passes/cmds/dft_tag.cc:128:16, inlined from 'void {anonymous}::DftTagWorker::resolve_overwrites()' at passes/cmds/dft_tag.cc:103:56: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'void {anonymous}::DftTagWorker::resolve_overwrites()': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const std::pair&; _U2 = Yosys::RTLIL::SigSpec; _T1 = std::pair; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = std::pair; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::DftTagWorker::divert_users(Yosys::RTLIL::SigBit, Yosys::RTLIL::SigBit)' at passes/cmds/dft_tag.cc:149:21, inlined from 'Yosys::RTLIL::SigSpec {anonymous}::DftTagWorker::divert_users(Yosys::RTLIL::SigSpec)' at passes/cmds/dft_tag.cc:128:16, inlined from 'void {anonymous}::DftTagWorker::resolve_overwrites()' at passes/cmds/dft_tag.cc:103:56: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void {anonymous}::DftTagWorker::resolve_overwrites()': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 53%] Building passes/sat/sat.o [ 54%] Building passes/sat/freduce.o [ 54%] Building passes/sat/eval.o [ 54%] Building passes/sat/sim.o [ 54%] Building passes/sat/miter.o [ 55%] Building passes/sat/expose.o [ 55%] Building passes/sat/assertpmux.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from passes/fsm/fsm_detect.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/fsm/fsm_detect.cc:23: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:475: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/hierarchy/hierarchy.cc:21: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/opt/opt_hier.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 55%] Building passes/sat/clk2fflogic.o [ 55%] Building passes/sat/async2sync.o [ 56%] Building passes/sat/formalff.o [ 56%] Building passes/sat/supercover.o [ 56%] Building passes/sat/fmcombine.o [ 56%] Building passes/sat/mutate.o In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Wire* const&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::Wire*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Wire* const&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::Wire*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 57%] Building passes/sat/cutpoint.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from passes/fsm/fsm_extract.cc:25: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/fsm/fsm_extract.cc:28: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:475: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 57%] Building passes/sat/fminit.o [ 57%] Building passes/sat/recover_names.o [ 57%] Building passes/sat/qbfsat.o [ 58%] Building passes/sat/synthprop.o [ 58%] Building passes/techmap/techmap.o [ 58%] Building passes/techmap/simplemap.o [ 59%] Building passes/techmap/dfflibmap.o [ 59%] Building passes/techmap/maccmap.o [ 59%] Building passes/techmap/booth.o [ 59%] Building passes/techmap/libparse.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/opt/opt_merge.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 60%] Building passes/techmap/libcache.o [ 60%] Building passes/techmap/abc.o [ 60%] Building passes/techmap/abc9.o [ 60%] Building passes/techmap/abc9_exe.o [ 61%] Building passes/techmap/abc9_ops.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/opt/muxpack.cc:21: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = std::vector]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair >; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair >]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::pair > >,std::pair > >::first.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = std::vector]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair >; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair >]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::pair > >,std::pair > >::first.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 61%] Building passes/techmap/abc_new.o [ 61%] Building passes/techmap/iopadmap.o [ 61%] Building passes/techmap/clkbufmap.o [ 62%] Building passes/techmap/hilomap.o [ 62%] Building passes/techmap/extract.o [ 62%] Building passes/techmap/extract_fa.o [ 62%] Building passes/techmap/extract_counter.o [ 63%] Building passes/techmap/extract_reduce.o [ 63%] Building passes/techmap/alumacc.o [ 63%] Building passes/techmap/dffinit.o In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)' at passes/fsm/fsm_extract.cc:412:96: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)' at passes/fsm/fsm_extract.cc:412:96: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 64%] Building passes/techmap/pmuxtree.o [ 64%] Building passes/techmap/bmuxmap.o [ 64%] Building passes/techmap/demuxmap.o [ 64%] Building passes/techmap/bwmuxmap.o [ 65%] Building passes/techmap/muxcover.o [ 65%] Building passes/techmap/aigmap.o [ 65%] Building passes/techmap/tribuf.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from kernel/rtlil.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/sat/fminit.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:117:30, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/sat/fminit.cc:164:31: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ passes/sat/fminit.cc: In member function 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/sat/fminit.cc:164:75: note: '' declared here 164 | ctrlsig_latched.push_back(SigSpec()); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:117:30, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/sat/fminit.cc:164:31: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ passes/sat/fminit.cc: In member function 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/sat/fminit.cc:164:75: note: '' declared here 164 | ctrlsig_latched.push_back(SigSpec()); | ^ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/sat/fminit.cc:164:31: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ passes/sat/fminit.cc: In member function 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/sat/fminit.cc:164:75: note: '' declared here 164 | ctrlsig_latched.push_back(SigSpec()); | ^ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::RTLIL::SigSpec; _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::RTLIL::SigSpec}; _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::RTLIL::SigSpec; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/sat/fminit.cc:164:31: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ passes/sat/fminit.cc: In member function 'virtual void {anonymous}::FminitPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/sat/fminit.cc:164:75: note: '' declared here 164 | ctrlsig_latched.push_back(SigSpec()); | ^ [ 65%] Building passes/techmap/lut2mux.o [ 66%] Building passes/techmap/lut2bmux.o [ 66%] Building passes/techmap/nlutmap.o [ 66%] Building passes/techmap/shregmap.o [ 66%] Building passes/techmap/deminout.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/proc/proc_dff.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/proc/proc_dff.cc:22: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 67%] Building passes/techmap/insbuf.o [ 67%] Building passes/techmap/bufnorm.o [ 67%] Building passes/techmap/attrmvcp.o [ 67%] Building passes/techmap/attrmap.o [ 68%] Building passes/techmap/zinit.o [ 68%] Building passes/techmap/dfflegalize.o [ 68%] Building passes/techmap/dffunmap.o [ 69%] Building passes/techmap/flowmap.o [ 69%] Building passes/techmap/extractinv.o [ 69%] Building passes/techmap/cellmatch.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/techmap/maccmap.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from passes/techmap/maccmap.cc:21: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 69%] Building passes/techmap/clockgate.o [ 70%] Building passes/techmap/constmap.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/techmap/dfflibmap.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 70%] Building passes/techmap/arith_tree.o [ 70%] Building passes/tests/test_autotb.o [ 70%] Building passes/tests/test_cell.o [ 71%] Building passes/tests/test_abcloop.o [ 71%] Building passes/tests/raise_error.o [ 71%] Building backends/aiger/aiger.o In file included from ./kernel/yosys_common.h:36, from ./kernel/rtlil.h:23, from ./passes/opt/opt_clean/opt_clean.h:20, from passes/opt/opt_clean/wires.cc:20: In function 'constexpr std::__optional_ne_t<_Tp, _Up> std::operator!=(const optional<_Tp>&, const optional<_Up>&) [with _Tp = __gnu_cxx::__normal_iterator >; _Up = __gnu_cxx::__normal_iterator >]', inlined from 'bool Yosys::ShardedVector::iterator::operator!=(const Yosys::ShardedVector::iterator&) const [with T = Yosys::RTLIL::Wire*]' at ./kernel/threading.h:374:52, inlined from 'void Yosys::hashlib::pool::insert(InputIterator, InputIterator) [with InputIterator = Yosys::ShardedVector::iterator; K = Yosys::RTLIL::Wire*; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:1126:16, inlined from '{anonymous}::WireDeleter::WireDeleter({anonymous}::UsedSignals&, bool, const Yosys::AnalysisContext&)' at passes/opt/opt_clean/wires.cc:503:25, inlined from 'bool Yosys::rmunused_module_signals(RTLIL::Module*, ParallelDispatchThreadPool::Subpool&, CleanRunContext&)' at passes/opt/opt_clean/wires.cc:566:55: /usr/include/c++/15.2.0/optional:1469:38: warning: '*(__gnu_cxx::__normal_iterator > >*)((char*)&first + offsetof(Yosys::ShardedVector::iterator, Yosys::ShardedVector::iterator::inner_it.std::optional<__gnu_cxx::__normal_iterator > > >::.std::_Optional_base<__gnu_cxx::__normal_iterator > >, true, true>::_M_payload.std::_Optional_payload<__gnu_cxx::__normal_iterator > >, true, true, true>::.std::_Optional_payload_base<__gnu_cxx::__normal_iterator > > >::_M_payload)).__gnu_cxx::__normal_iterator >::_M_current' may be used uninitialized [-Wmaybe-uninitialized] 1469 | || (static_cast(__lhs) && *__lhs != *__rhs); | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ passes/opt/opt_clean/wires.cc: In function 'bool Yosys::rmunused_module_signals(RTLIL::Module*, ParallelDispatchThreadPool::Subpool&, CleanRunContext&)': passes/opt/opt_clean/wires.cc:536:6: note: '*(__gnu_cxx::__normal_iterator > >*)((char*)&first + offsetof(Yosys::ShardedVector::iterator, Yosys::ShardedVector::iterator::inner_it.std::optional<__gnu_cxx::__normal_iterator > > >::.std::_Optional_base<__gnu_cxx::__normal_iterator > >, true, true>::_M_payload.std::_Optional_payload<__gnu_cxx::__normal_iterator > >, true, true, true>::.std::_Optional_payload_base<__gnu_cxx::__normal_iterator > > >::_M_payload)).__gnu_cxx::__normal_iterator >::_M_current' was declared here 536 | bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx) | ^~~~~~~~~~~~~~~~~~~~~~~ [ 71%] Building backends/aiger/xaiger.o [ 72%] Building backends/aiger2/aiger.o [ 72%] Building backends/blif/blif.o [ 72%] Building backends/btor/btor.o [ 72%] Building backends/cxxrtl/cxxrtl_backend.o [ 73%] Building backends/edif/edif.o [ 73%] Building backends/firrtl/firrtl.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/opt/share.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/satgen.h:26, from ./kernel/qcsat.h:23, from passes/opt/share.cc:21: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 73%] Building backends/functional/cxx.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from ./kernel/sigtools.h:23, from passes/techmap/booth.cc:58: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from passes/techmap/booth.cc:60: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 73%] Building backends/functional/smtlib.o [ 74%] Building backends/functional/smtlib_rosette.o [ 74%] Building backends/functional/test_generic.o [ 74%] Building backends/intersynth/intersynth.o [ 75%] Building backends/jny/jny.o [ 75%] Building backends/json/json.o [ 75%] Building backends/rtlil/rtlil_backend.o [ 75%] Building backends/simplec/simplec.o [ 76%] Building backends/smt2/smt2.o [ 76%] Building backends/smv/smv.o [ 76%] Building backends/spice/spice.o [ 76%] Building backends/table/table.o [ 77%] Building backends/verilog/verilog_backend.o [ 77%] Building techlibs/achronix/synth_achronix.o [ 77%] Building techlibs/analogdevices/synth_analogdevices.o [ 77%] Building techlibs/anlogic/synth_anlogic.o [ 78%] Building techlibs/anlogic/anlogic_eqn.o [ 78%] Building techlibs/anlogic/anlogic_fixcarry.o [ 78%] Building techlibs/common/synth.o [ 78%] Building techlibs/common/prep.o [ 79%] Building techlibs/common/opensta.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/sat/eval.cc:23: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/sat/eval.cc:25: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 79%] Building techlibs/common/sdc_expand.o [ 79%] Building techlibs/coolrunner2/synth_coolrunner2.o [ 80%] Building techlibs/coolrunner2/coolrunner2_sop.o [ 80%] Building techlibs/coolrunner2/coolrunner2_fixup.o [ 80%] Building techlibs/easic/synth_easic.o [ 80%] Building techlibs/efinix/synth_efinix.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/techmap/extract_fa.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/techmap/extract_fa.cc:22: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 81%] Building techlibs/efinix/efinix_fixcarry.o [ 81%] Building techlibs/fabulous/synth_fabulous.o [ 81%] Building techlibs/gatemate/synth_gatemate.o [ 81%] Building techlibs/gatemate/gatemate_foldinv.o [ 82%] Building techlibs/gowin/synth_gowin.o [ 82%] Building techlibs/greenpak4/synth_greenpak4.o [ 82%] Building techlibs/greenpak4/greenpak4_dffinv.o [ 82%] Building techlibs/ice40/synth_ice40.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/sat/qbfsat.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/sat/qbfsat.cc:22: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from ./kernel/celltypes.h:23, from passes/techmap/cellmatch.cc:1: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/techmap/cellmatch.cc:5: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 83%] Building techlibs/ice40/ice40_braminit.o [ 83%] Building techlibs/ice40/ice40_opt.o [ 83%] Building techlibs/ice40/ice40_dsp.o [ 83%] Building techlibs/ice40/ice40_wrapcarry_pm.h [ 84%] Building techlibs/intel/synth_intel.o [ 84%] Building techlibs/intel_alm/synth_intel_alm.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/sat/recover_names.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/sat/recover_names.cc:22: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 84%] Building techlibs/lattice/synth_lattice.o [ 85%] Building techlibs/lattice/lattice_gsr.o [ 85%] Building techlibs/lattice/lattice_dsp_nexus_pm.h [ 85%] Building techlibs/microchip/synth_microchip.o [ 85%] Building techlibs/microchip/microchip_dffopt.o [ 85%] Building techlibs/microchip/microchip_dsp_pm.h [ 85%] Building techlibs/microchip/microchip_dsp_CREG_pm.h [ 85%] Building techlibs/microchip/microchip_dsp_cascade_pm.h [ 86%] Building techlibs/nanoxplore/synth_nanoxplore.o [ 86%] Building techlibs/nanoxplore/nx_carry.o [ 86%] Building techlibs/quicklogic/synth_quicklogic.o [ 87%] Building techlibs/quicklogic/ql_bram_merge.o In file included from ./kernel/yosys.h:43, from techlibs/anlogic/anlogic_fixcarry.cc:20: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::fix_carry_chain(Yosys::RTLIL::Module*)' at techlibs/anlogic/anlogic_fixcarry.cc:49:16: ./kernel/rtlil.h:1610:86: warning: 'o.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1610 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/anlogic/anlogic_fixcarry.cc: In function 'void {anonymous}::fix_carry_chain(Yosys::RTLIL::Module*)': techlibs/anlogic/anlogic_fixcarry.cc:48:41: note: 'o' declared here 48 | SigSpec o = cell->getPort(ID(o)); | ^ [ 87%] Building techlibs/quicklogic/ql_bram_types.o [ 87%] Building techlibs/quicklogic/ql_dsp_simd.o [ 87%] Building techlibs/quicklogic/ql_dsp_io_regs.o [ 88%] Building techlibs/quicklogic/ql_ioff.o [ 88%] Building techlibs/quicklogic/ql_dsp_macc_pm.h [ 88%] Building techlibs/sf2/synth_sf2.o [ 88%] Building techlibs/xilinx/synth_xilinx.o [ 89%] Building techlibs/xilinx/xilinx_dffopt.o [ 89%] Building techlibs/xilinx/xilinx_dsp_pm.h [ 89%] Building techlibs/xilinx/xilinx_dsp48a_pm.h [ 89%] Building techlibs/xilinx/xilinx_dsp_CREG_pm.h In file included from ./kernel/yosys.h:43, from techlibs/gatemate/gatemate_foldinv.cc:21: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::FoldInvWorker::fold_input_inverters()' at techlibs/gatemate/gatemate_foldinv.cc:109:28: ./kernel/rtlil.h:1610:86: warning: 'sig.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1610 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/gatemate/gatemate_foldinv.cc: In member function 'void {anonymous}::FoldInvWorker::fold_input_inverters()': techlibs/gatemate/gatemate_foldinv.cc:108:22: note: 'sig' declared here 108 | auto sig = cell->getPort(ipin.first); | ^~~ [ 89%] Building techlibs/xilinx/xilinx_dsp_cascade_pm.h [ 89%] Building techlibs/xilinx/xilinx_srl.o [ 99%] Building yosys-config [ 99%] Building passes/techmap/filterlib.o [ 99%] Building yosys-smtbmc [ 99%] Building yosys-witness [ 99%] Building share/include/kernel/binding.h [ 99%] Building share/include/kernel/bitpattern.h [ 99%] Building share/include/kernel/cellaigs.h [ 99%] Building share/include/kernel/celledges.h [ 99%] Building share/include/kernel/celltypes.h [ 99%] Building share/include/kernel/newcelltypes.h [ 99%] Building share/include/kernel/consteval.h [ 99%] Building share/include/kernel/constids.inc [ 99%] Building share/include/kernel/cost.h [ 99%] Building share/include/kernel/drivertools.h [ 99%] Building share/include/kernel/ff.h [ 99%] Building share/include/kernel/ffinit.h [ 99%] Building share/include/kernel/ffmerge.h [ 99%] Building share/include/kernel/fmt.h [ 99%] Building share/include/kernel/fstdata.h [ 99%] Building share/include/kernel/gzip.h [ 99%] Building share/include/kernel/hashlib.h [ 99%] Building share/include/kernel/io.h [ 99%] Building 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share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h [ 99%] Building share/python3/smtio.py [ 99%] Building share/python3/ywio.py [ 99%] Building share/achronix/speedster22i/cells_sim.v [ 99%] Building share/achronix/speedster22i/cells_map.v [ 99%] Building share/analogdevices/cells_map.v [ 99%] Building share/analogdevices/cells_sim.v [ 99%] Building share/analogdevices/lutrams.txt [ 99%] Building share/analogdevices/lutrams_map.v [ 99%] Building share/analogdevices/brams_defs.vh [ 99%] Building share/analogdevices/brams.txt [ 99%] Building share/analogdevices/brams_map.v [ 99%] Building share/analogdevices/arith_map.v [ 99%] Building share/analogdevices/ff_map.v [ 99%] Building share/analogdevices/lut_map.v [ 99%] Building share/analogdevices/mux_map.v [ 99%] Building share/analogdevices/dsp_map.v [ 99%] Building share/analogdevices/abc9_model.v [ 99%] Building share/anlogic/cells_map.v [ 99%] Building share/anlogic/arith_map.v [ 99%] Building share/anlogic/cells_sim.v [ 99%] Building share/anlogic/eagle_bb.v [ 99%] Building share/anlogic/lutrams.txt [ 99%] Building share/anlogic/lutrams_map.v [ 99%] Building share/anlogic/brams.txt [ 99%] Building share/anlogic/brams_map.v [ 99%] Building share/simlib.v [ 99%] Building share/simcells.v [ 99%] Building share/techmap.v [ 99%] Building share/smtmap.v [ 99%] Building share/pmux2mux.v [ 99%] Building share/adff2dff.v [ 99%] Building share/dff2ff.v [ 99%] Building share/gate2lut.v [ 99%] Building share/cmp2lut.v [ 99%] Building share/mul2dsp.v [ 99%] Building share/abc9_model.v [ 99%] Building share/abc9_map.v [ 99%] Building share/abc9_unmap.v [ 99%] Building share/cmp2lcu.v [ 99%] Building share/cmp2softlogic.v [ 99%] Building share/choices/kogge-stone.v [ 99%] Building share/choices/han-carlson.v [ 99%] Building share/choices/sklansky.v [ 99%] Building share/coolrunner2/cells_latch.v [ 99%] Building share/coolrunner2/cells_sim.v [ 99%] Building share/coolrunner2/cells_counter_map.v [ 99%] Building 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99%] Building share/gatemate/brams.txt [ 99%] Building share/gatemate/brams_init_20.vh [ 99%] Building share/gatemate/brams_init_40.vh [ 99%] Building share/gatemate/inv_map.v [ 99%] Building techlibs/gatemate/lut_tree_lib.mk [ 99%] Building share/gowin/cells_map.v [ 99%] Building share/gowin/cells_sim.v [ 99%] Building share/gowin/cells_latch.v [ 99%] Building share/gowin/cells_xtra_gw1n.v [ 99%] Building share/gowin/cells_xtra_gw2a.v [ 99%] Building share/gowin/cells_xtra_gw5a.v [ 99%] Building share/gowin/arith_map.v [ 99%] Building share/gowin/brams_map.v [ 99%] Building share/gowin/brams_map_gw5a.v [ 99%] Building share/gowin/brams.txt [ 99%] Building share/gowin/lutrams_map.v [ 99%] Building share/gowin/lutrams.txt [ 99%] Building share/gowin/dsp_map.v [ 99%] Building share/greenpak4/cells_blackbox.v [ 99%] Building share/greenpak4/cells_latch.v [ 99%] Building share/greenpak4/cells_map.v [ 99%] Building share/greenpak4/cells_sim.v [ 99%] Building share/greenpak4/cells_sim_ams.v [ 99%] Building share/greenpak4/cells_sim_digital.v [ 99%] Building share/greenpak4/cells_sim_wip.v [ 99%] Building share/greenpak4/gp_dff.lib [ 99%] Building share/ice40/arith_map.v [ 99%] Building share/ice40/cells_map.v [ 99%] Building share/ice40/ff_map.v [ 99%] Building share/ice40/cells_sim.v [ 99%] Building share/ice40/latches_map.v [ 99%] Building share/ice40/brams.txt [ 99%] Building share/ice40/brams_map.v [ 99%] Building share/ice40/spram.txt [ 99%] Building share/ice40/spram_map.v [ 99%] Building share/ice40/dsp_map.v [ 99%] Building share/ice40/abc9_model.v [ 99%] Building share/intel/common/m9k_bb.v [ 99%] Building share/intel/common/altpll_bb.v [ 99%] Building share/intel/common/brams_m9k.txt [ 99%] Building share/intel/common/brams_map_m9k.v [ 99%] Building share/intel/common/ff_map.v [ 99%] Building share/intel/max10/cells_sim.v [ 99%] Building share/intel/cyclone10lp/cells_sim.v [ 99%] Building share/intel/cycloneiv/cells_sim.v [ 99%] Building share/intel/cycloneive/cells_sim.v [ 99%] Building share/intel/max10/cells_map.v [ 99%] Building share/intel/cyclone10lp/cells_map.v [ 99%] Building share/intel/cycloneiv/cells_map.v [ 99%] Building share/intel/cycloneive/cells_map.v [ 99%] Building share/intel_alm/common/abc9_map.v [ 99%] Building share/intel_alm/common/abc9_unmap.v [ 99%] Building share/intel_alm/common/abc9_model.v [ 99%] Building share/intel_alm/common/alm_map.v [ 99%] Building share/intel_alm/common/alm_sim.v [ 99%] Building share/intel_alm/common/arith_alm_map.v [ 99%] Building share/intel_alm/common/dff_map.v [ 99%] Building share/intel_alm/common/dff_sim.v [ 99%] Building share/intel_alm/common/dsp_sim.v [ 99%] Building share/intel_alm/common/dsp_map.v [ 99%] Building share/intel_alm/common/mem_sim.v [ 99%] Building share/intel_alm/common/misc_sim.v [ 99%] Building share/intel_alm/cyclonev/cells_sim.v [ 99%] Building share/intel_alm/common/bram_m10k.txt [ 99%] Building share/intel_alm/common/bram_m10k_map.v In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/techmap/flowmap.cc:98: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from passes/techmap/flowmap.cc:101: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 99%] Building share/intel_alm/common/lutram_mlab.txt [ 99%] Building share/intel_alm/common/megafunction_bb.v [ 99%] Building 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[ 99%] Building share/nexus/cells_xtra.v [ 99%] Building share/microchip/arith_map.v [ 99%] Building share/microchip/cells_map.v [ 99%] Building share/microchip/cells_sim.v [ 99%] Building share/microchip/polarfire_dsp_map.v [ 99%] Building share/microchip/brams_defs.vh [ 99%] Building share/microchip/LSRAM_map.v [ 99%] Building share/microchip/LSRAM.txt [ 99%] Building share/microchip/uSRAM_map.v [ 99%] Building share/microchip/uSRAM.txt [ 99%] Building share/nanoxplore/arith_map.v [ 99%] Building share/nanoxplore/brams_init.vh [ 99%] Building share/nanoxplore/brams_map.v [ 99%] Building share/nanoxplore/brams.txt [ 99%] Building share/nanoxplore/cells_bb.v [ 99%] Building share/nanoxplore/cells_bb_l.v [ 99%] Building share/nanoxplore/cells_bb_m.v [ 99%] Building share/nanoxplore/cells_bb_u.v [ 99%] Building share/nanoxplore/cells_map.v [ 99%] Building share/nanoxplore/cells_sim.v [ 99%] Building share/nanoxplore/cells_sim_l.v [ 99%] Building share/nanoxplore/cells_sim_m.v [ 99%] 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99%] Building share/quicklogic/pp3/abc9_map.v [ 99%] Building share/quicklogic/pp3/abc9_unmap.v [ 99%] Building share/quicklogic/qlf_k6n10f/arith_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/libmap_brams.txt [ 99%] Building share/quicklogic/qlf_k6n10f/libmap_brams_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/brams_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/brams_sim.v [ 99%] Building techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/cells_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/ffs_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_final_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v [ 99%] Building share/quicklogic/qlf_k6n10f/ufifo_ctl.v [ 99%] Building share/quicklogic/qlf_k6n10f/sram1024x18_mem.v [ 99%] Building share/sf2/arith_map.v [ 99%] Building share/sf2/cells_map.v [ 99%] Building share/sf2/cells_sim.v [ 99%] Building share/xilinx/cells_map.v [ 99%] Building share/xilinx/cells_sim.v [ 99%] Building share/xilinx/cells_xtra.v [ 99%] Building share/xilinx/lutrams_xcv.txt [ 99%] Building share/xilinx/lutrams_xcv_map.v [ 99%] Building share/xilinx/lutrams_xc5v.txt [ 99%] Building share/xilinx/lutrams_xcu.txt [ 99%] Building share/xilinx/lutrams_xc5v_map.v [ 99%] Building share/xilinx/brams_xcv.txt [ 99%] Building share/xilinx/brams_xcv_map.v [ 99%] Building share/xilinx/brams_defs.vh [ 99%] Building share/xilinx/brams_xc2v.txt [ 99%] Building share/xilinx/brams_xc2v_map.v [ 99%] Building share/xilinx/brams_xc3sda.txt [ 99%] Building share/xilinx/brams_xc3sda_map.v [ 99%] Building share/xilinx/brams_xc4v.txt [ 99%] Building share/xilinx/brams_xc4v_map.v [ 99%] Building share/xilinx/brams_xc5v_map.v [ 99%] Building share/xilinx/brams_xc6v_map.v [ 99%] Building share/xilinx/brams_xcu_map.v [ 99%] Building share/xilinx/urams.txt [ 99%] Building share/xilinx/urams_map.v [ 99%] Building share/xilinx/arith_map.v [ 99%] Building share/xilinx/ff_map.v [ 99%] Building share/xilinx/lut_map.v [ 99%] Building share/xilinx/mux_map.v [ 99%] Building share/xilinx/xc3s_mult_map.v [ 99%] Building share/xilinx/xc3sda_dsp_map.v [ 99%] Building share/xilinx/xc6s_dsp_map.v [ 99%] Building share/xilinx/xc4v_dsp_map.v [ 99%] Building share/xilinx/xc5v_dsp_map.v [ 99%] Building share/xilinx/xc7_dsp_map.v [ 99%] Building share/xilinx/xcu_dsp_map.v [ 99%] Building share/xilinx/abc9_model.v In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/tests/test_cell.cc:21: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/satgen.h:26, from passes/tests/test_cell.cc:22: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 99%] Building kernel/version_7f8fdfd8d7bc08c749a2a969388d3425d4f369d5.o [ 99%] Building pyosys/wrappers.o [ 99%] Building kernel/register.o [ 99%] Building frontends/verilog/verilog_parser.tab.o In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::FoldInvWorker::fold_output_inverters()' at techlibs/gatemate/gatemate_foldinv.cc:147:24: ./kernel/rtlil.h:1610:86: warning: 'o_sig.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1610 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/gatemate/gatemate_foldinv.cc: In member function 'void {anonymous}::FoldInvWorker::fold_output_inverters()': techlibs/gatemate/gatemate_foldinv.cc:146:18: note: 'o_sig' declared here 146 | auto o_sig = cell->getPort(ID::O); | ^~~~~ [ 99%] Building frontends/verilog/verilog_lexer.cc [ 99%] Building frontends/verilog/preproc.o [ 99%] Building frontends/verilog/verilog_frontend.o [ 99%] Building passes/opt/peepopt.o [ 99%] Building passes/pmgen/test_pmgen.o [ 99%] Building techlibs/ice40/ice40_wrapcarry.o [ 99%] Building techlibs/lattice/lattice_dsp_nexus.o [ 99%] Building techlibs/microchip/microchip_dsp.o [ 99%] Building techlibs/quicklogic/ql_dsp_macc.o [ 99%] Building techlibs/xilinx/xilinx_dsp.o [ 99%] Building share/gatemate/lut_tree_cells.genlib [ 99%] Building share/gatemate/lut_tree_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/bram_types_sim.v [ 99%] Building frontends/verilog/verilog_lexer.o In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from kernel/rtlil.cc:21: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24, from passes/techmap/abc9_ops.cc:21: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'void {anonymous}::prep_delays(Yosys::RTLIL::Design*, bool)' at passes/techmap/abc9_ops.cc:682:26: ./kernel/rtlil.h:1610:86: warning: 'rhs.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1610 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ passes/techmap/abc9_ops.cc: In function 'void {anonymous}::prep_delays(Yosys::RTLIL::Design*, bool)': passes/techmap/abc9_ops.cc:681:30: note: 'rhs' declared here 681 | auto rhs = cell->getPort(i.first.name); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from techlibs/quicklogic/ql_dsp_simd.cc:19: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)' at techlibs/quicklogic/ql_dsp_simd.cc:269:27: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:475: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)' at techlibs/quicklogic/ql_dsp_simd.cc:269:27: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/techmap/abc.cc:44: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:586:41, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 6; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<6, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<7, Yosys::RTLIL::SigSpec>::.std::_Head_base<7, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:586:41, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 6; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<6, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<7, Yosys::RTLIL::SigSpec>::.std::_Head_base<7, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<5, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<5, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<3, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<3, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<1, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:996:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<1, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)' at passes/techmap/abc9_ops.cc:904:53: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23, inlined from 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)' at passes/techmap/abc9_ops.cc:904:53: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc: In function 'void pyosys::pybind11_init_libyosys(pybind11::module_&)': /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:562:90: warning: 'bool Yosys::RTLIL::IdString::in(const Yosys::hashlib::pool&) const' is deprecated [-Wdeprecated-declarations] In file included from ./kernel/binding.h:23, from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:21: ./kernel/rtlil.h:676:13: note: declared here 676 | inline bool RTLIL::IdString::in(const pool &rhs) const { return rhs.count(*this) != 0; } | ^~~~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23, from backends/cxxrtl/cxxrtl_backend.cc:20: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from '{anonymous}::WireType::WireType({anonymous}::WireType&&)' at backends/cxxrtl/cxxrtl_backend.cc:649:8, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::Wire* const&; _U2 = {anonymous}::WireType; _T1 = const Yosys::RTLIL::Wire*; _T2 = {anonymous}::WireType]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(::WireType, ::WireType::sig_subst.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from '{anonymous}::WireType::WireType({anonymous}::WireType&&)' at backends/cxxrtl/cxxrtl_backend.cc:649:8, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::Wire* const&; _U2 = {anonymous}::WireType; _T1 = const Yosys::RTLIL::Wire*; _T2 = {anonymous}::WireType]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(::WireType, ::WireType::sig_subst.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 99%] Building yosys-filterlib kernel/register.cc: In constructor 'Yosys::CellHelpMessages::CellHelpMessages()': kernel/register.cc:743:9: note: variable tracking size limit exceeded with '-fvar-tracking-assignments', retrying without 743 | CellHelpMessages() { | ^~~~~~~~~~~~~~~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23: In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:464:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:828:23: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:828:60: note: '' declared here 828 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'constexpr std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'constexpr std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1295:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/consteval.h:26, from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:27: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In constructor 'constexpr Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1479:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1477:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'constexpr _Tp* std::construct_at(_Tp*, _Args&& ...) [with _Tp = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:110:9, inlined from 'static constexpr void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:676:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'constexpr void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1295:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1295 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from /usr/lib/python3.14/site-packages/pybind11/include/pybind11/attr.h:13, from /usr/lib/python3.14/site-packages/pybind11/include/pybind11/detail/class.h:12, from /usr/lib/python3.14/site-packages/pybind11/include/pybind11/pybind11.h:12, from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:22: /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc: In function 'void pyosys::pybind11_init_libyosys(pybind11::module_&)': /usr/lib/python3.14/site-packages/pybind11/include/pybind11/detail/common.h:495:26: note: variable tracking size limit exceeded with '-fvar-tracking-assignments', retrying without 495 | void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ \ | ^~~~~~~~~~~~~~ /usr/lib/python3.14/site-packages/pybind11/include/pybind11/detail/common.h:370:40: note: in definition of macro 'PYBIND11_CONCAT' 370 | #define PYBIND11_CONCAT(first, second) first##second | ^~~~~ /usr/lib/python3.14/site-packages/pybind11/include/pybind11/detail/common.h:539:5: note: in expansion of macro 'PYBIND11_MODULE_EXEC' 539 | PYBIND11_MODULE_EXEC(name, variable) | ^~~~~~~~~~~~~~~~~~~~ /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:168:9: note: in expansion of macro 'PYBIND11_MODULE' 168 | PYBIND11_MODULE(libyosys, m) { | ^~~~~~~~~~~~~~~ [100%] Building yosys [100%] Building libyosys.so Build successful. [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests' make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src' mkdir -p /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/ /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/opt/ /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/techmap/ mkdir -p /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/ /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/opt/ /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/techmap/ g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/techmap/libparseTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//techmap/libparseTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/logTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/logTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/rtlilTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/rtlilTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/ioTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/ioTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/modindexTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/modindexTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/cellTypesTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/cellTypesTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/sigspecRemove2Test.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/sigspecRemove2Test.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/bitpatternTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/bitpatternTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/sigspecExtractTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/sigspecExtractTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/rtlilStringTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/rtlilStringTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/threadingTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/threadingTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/hashTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//kernel/hashTest.cc g++ -o /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/opt/optDffFindComplementaryPatternTest.o -c -I/home/buildozer/aports/testing/yosys/src -Os -fstack-clash-protection -Wformat -Werror=format-security -D_GLIBCXX_ASSERTIONS=1 -D_LIBCPP_ENABLE_THREAD_SAFETY_ANNOTATIONS=1 -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST -Wall -Wextra -Werror=unused -ggdb -I. -I./ -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.66\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=66 -DYOSYS_COMMIT=0.66 -std=c++20 -O3 -I-I/usr/include/python3.14 -I/usr/lib/python3.14/site-packages/pybind11/include -DYOSYS_ENABLE_PYTHON -I/usr/include/python3.14 -I/usr/include/python3.14 -DYOSYS_ENABLE_PYTHON -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_THREADS -DYOSYS_ENABLE_ABC /home/buildozer/aports/testing/yosys/src/tests/unit//opt/optDffFindComplementaryPatternTest.cc make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/hana' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/rpc' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/cxxrtl' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memories' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memfile' xprop PRNG seed: 2554669175 opt_share PRNG seed: 5209661373689658817 share PRNG seed: 7684793139419132869 fsm PRNG seed: 2781244755959276328 make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple' PASS parent_content1 PASS parent_content2_temp make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/share' PASS code_hdl_models_arbiter_tb.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' PASS parent_content2_full PASS same_content1 PASS same_content2 PASS child_content1 bram PRNG seed: 606189 PASS uut_00000.ys PASS uut_00000.ys PASS uut_00001.ys PASS frontend.py PASS exec.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/rpc' ...passed tests in ./rpc PASS child_content2_temp PASS uut_00001.ys PASS uut_00002.ys PASS fail_empty_filename PASS child_content2_direct PASS uut_00002.ys PASS uut_00003.ys Generate FST for sim models Test tb_sdffce Test tb_adff Test tb_aldff Test tb_sdff Test tb_dlatch Test tb_dff Test tb_dffsr Test tb_dffe Test tb_adffe Test tb_adlatch Test tb_sdffe Test tb_dlatchsr Test tb_aldffe PASS fail_missing_file make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memfile' ...passed tests in ./memfile PASS uut_00004.ys PASS uut_00004.ys PASS uut_00005.ys PASS uut_00006.ys PASS uut_00007.ys PASS uut_00003.ys PASS test_simulation_buffer.v realmath PRNG seed: 7169393023443150623 PASS uut_00008.ys PASS arrays01.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' PASS code_hdl_models_arbiter.v PASS test_simulation_vlib.v PASS uut_00006.ys PASS always01.v PASS always02.v PASS uut_00005.ys PASS uut_00009.ys PASS uut_00007.ys PASS code_hdl_models_d_ff_gates.v PASS always03.v PASS code_hdl_models_decoder_2to4_gates.v PASS code_hdl_models_d_latch_gates.v PASS aes_kexp128.v PASS uut_00010.ys PASS uut_00008.ys PASS always01.v PASS code_hdl_models_GrayCounter.v PASS uut_00011.ys PASS test_simulation_seq.v PASS code_hdl_models_clk_div.v PASS uut_00009.ys PASS code_hdl_models_dff_async_reset.v PASS code_hdl_models_encoder_4to2_gates.v PASS uut_00010.ys PASS uut_00012.ys PASS code_hdl_models_full_adder_gates.v PASS code_hdl_models_dff_sync_reset.v PASS always02.v PASS code_hdl_models_decoder_using_assign.v PASS code_hdl_models_full_subtracter_gates.v PASS code_hdl_models_decoder_using_case.v PASS uut_00013.ys PASS uut_00011.ys PASS code_hdl_models_clk_div_45.v PASS aes_kexp128.v PASS arraycells.v PASS uut_00014.ys PASS uut_00012.ys PASS arrays02.sv PASS test_parse2synthtrans.v PASS arrays01.v PASS uut_00013.ys PASS test_simulation_xnor.v PASS test_simulation_nor.v PASS always03.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bram' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' PASS uut_00015.ys PASS test_simulation_xor.v PASS uut_00014.ys PASS code_hdl_models_gray_counter.v PASS code_hdl_models_encoder_using_if.v PASS uut_00016.ys PASS code_hdl_models_encoder_using_case.v PASS firrtl_938.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/svinterfaces' PASS test_simulation_nand.v PASS uut_00017.ys PASS uut_00015.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/xprop' PASS uut_00016.ys PASS arraycells.v PASS uut_00017.ys PASS load_and_derive.ys PASS cxxrtl_value PASS uut_00005.ys PASS uut_00018.ys PASS arrays02.sv PASS uut_00018.ys PASS implicit_en.v PASS test_simulation_or.v PASS uut_00019.ys PASS uut_00019.ys PASS test_simulation_inc.v PASS attrib01_module.v PASS no_implicit_en.v PASS uut_00020.ys PASS uut_00020.ys PASS test_parser.v PASS test_simulation_and.v PASS uut_00006.ys PASS uut_00021.ys PASS uut_00021.ys PASS attrib01_module.v PASS uut_00022.ys PASS attrib02_port_decl.v PASS positional_args.ys PASS uut_00023.ys PASS attrib08_mod_inst.v PASS async_small PASS test_simulation_sop.v PASS uut_00001.ys PASS attrib02_port_decl.v PASS uut_00023.ys PASS attrib03_parameter.v PASS attrib04_net_var.v PASS issue00335.v PASS attrib06_operator_suffix.v PASS sync_big PASS code_hdl_models_half_adder_gates.v PASS uut_00025.ys PASS resolve_types.ys PASS shared_ports.v PASS sync_small PASS sync_big_sdp PASS uut_00024.ys PASS sync_small_block PASS async_small_block PASS uut_00025.ys PASS uut_00026.ys PASS uut_00027.ys PASS uut_00028.ys PASS attrib03_parameter.v PASS test_simulation_decoder.v PASS attrib09_case.v PASS simple_sram_byte_en.v PASS code_hdl_models_lfsr.v PASS uut_00024.ys PASS read_two_mux.v PASS test_simulation_always.v PASS test_simulation_techmap.v PASS svinterface1 make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/svinterfaces' ...passed tests in ./svinterfaces PASS issue00710.v PASS read_arst.v PASS uut_00026.ys PASS attrib04_net_var.v PASS bram_00_01 PASS cxxrtl_unconnected_output PASS uut_00027.ys PASS uut_00028.ys PASS bram_00_02 PASS arrays03.sv PASS uut_00003.ys PASS uut_00002.ys PASS uut_00010.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/select' PASS code_hdl_models_mux_2to1_gates.v PASS bram_00_03 PASS uut_00029.ys PASS code_hdl_models_mux_using_case.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/peepopt' PASS boxes_equals_name.ys PASS code_hdl_models_mux_using_assign.v PASS code_hdl_models_mux_using_if.v PASS case_expr_const.v PASS code_hdl_models_lfsr_updown.v PASS uut_00030.ys PASS uut_00004.ys PASS boxes_equals_operators.ys PASS boxes_equals_pattern.ys PASS uut_00008.ys PASS wide_thru_priority.v PASS boxes_equals_wildcard.ys PASS attrib08_mod_inst.v PASS uut_00031.ys PASS code_hdl_models_parity_using_assign.v PASS sync_small_block_attr PASS boxes_import.ys PASS code_hdl_models_one_hot_cnt.v PASS uut_00032.ys PASS code_hdl_models_parity_using_bitwise.v PASS xprop_not_3s_5 PASS init_lut_zeros_zero PASS uut_00000.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/proc' PASS init_lut_val_any PASS init_lut_zeros_any PASS boxes_no_equals_clean.ys PASS uut_00033.ys PASS boxes_no_equals.ys PASS boxes_setattr.ys PASS bug2619.ys PASS init_lut_val_zero PASS test_simulation_mux.v PASS bug2656.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/blif' PASS uut_00034.ys PASS bug2962.ys PASS bug4712.ys PASS boxes_stack.ys PASS internal_selects.ys PASS amber23_sram_byte_en.v PASS bug2729.ys PASS uut_00035.ys PASS bug5572.ys PASS attrib06_operator_suffix.v PASS attrib09_case.v PASS list_mod.ys PASS wide_read_async.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch' PASS bug3374.ys PASS mod-attribute.ys PASS intel_alm_cyclonev_cells_sim PASS bram_00_04 PASS trans_addr_enable.v PASS bug_1268.ys PASS uut_00036.ys PASS quicklogic_pp3_cells_sim PASS bug3385.ys PASS carryadd.v PASS no_warn_assert.ys PASS wide_all.v PASS wide_read_sync.v PASS case_attr.ys PASS quicklogic_qlf_k6n10f_cells_sim PASS xilinx_cells_sim PASS uut_00037.ys PASS init_lut_val_no_undef PASS trans_sp.v PASS no_warn_prefixed_empty_select_arg.ys PASS no_warn_prefixed_arg_memb.ys PASS gatesi.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/blif' ...passed tests in ./blif PASS clean_undef_case.ys PASS quicklogic_common_cells_sim PASS achronix_speedster22i_cells_sim PASS init_lut_x_none PASS code_hdl_models_parallel_crc.v PASS arrays03.sv PASS nanoxplore_cells_sim PASS unset.ys PASS case_expr_extend.sv PASS init_lut_val2_no_undef PASS uut_00038.ys PASS analogdevices_cells_sim PASS wide_read_trans.v PASS init_lut_val2_any PASS proc_dff.ys PASS unset2.ys PASS sf2_cells_sim PASS trans_sdp.v PASS case_expr_non_const.v PASS gowin_cells_sim PASS uut_00039.ys PASS warn_empty_select_arg.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/select' PASS coolrunner2_cells_sim ...passed tests in ./select make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/fmt' PASS greenpak4_cells_sim PASS xprop_pos_3s_5 PASS case_expr_query.sv PASS efinix_cells_sim PASS wide_read_mixed.v PASS init_lut_x_zero PASS anlogic_cells_sim PASS xprop_and_1u1_1 PASS gatemate_cells_sim PASS proc_rom.ys PASS uut_00041.ys PASS const_branch_finish.v PASS init_lut_x_any make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/liberty' PASS initial_display PASS uut_00042.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/aiger' PASS rmdead.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/proc' ...passed tests in ./proc PASS ice40_cells_sim_ICE40_HX PASS wide_write.v make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memories' ...passed tests in ./memories PASS code_hdl_models_parity_using_function.v PASS ice40_cells_sim_ICE40_LP PASS ice40_cells_sim_ICE40_U PASS always_display_clk PASS init_lut_x_no_undef PASS uut_00012.ys PASS ram_18b2B make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/alumacc' PASS microchip_cells_sim All Makefiles generated. PASS case_expr_extend.sv PASS intel_cyclone10lp_cells_sim PASS intel_max10_cells_sim PASS const_branch_finish.v PASS and_to_bad_out.aag PASS xprop_neg_3s_5 PASS intel_cycloneiv_cells_sim PASS case_expr_query.sv PASS case_expr_non_const.v PASS case_expr_const.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/analogdevices' PASS intel_cycloneive_cells_sim PASS and_.aag PASS XNOR2X1.lib PASS ram_9b1B PASS carryadd.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' PASS always_display_clk_rst PASS simcells PASS macc_infer_n_unmap.ys PASS busdef.lib PASS simlib make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch' ...passed tests in ./arch PASS macc_b_port_compat.ys PASS uut_00040.ys PASS buffer.aag PASS uut_00043.ys PASS always_display_star PASS constpower.v PASS basic.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/alumacc' ...passed tests in ./alumacc PASS uut_00044.ys PASS xprop_and_1s1_2 PASS const_fold_func.v PASS ram_4b1B PASS const_fold_func.v PASS always_display_clk_en PASS uut_00045.ys PASS cnt1.aag PASS xprop_or_1s1_2 PASS code_hdl_models_rom_using_case.v PASS xprop_xor_1u1_1 PASS cnt1e.aag PASS dff.lib PASS uut_00047.ys PASS uut_00046.ys PASS uut_00048.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' PASS always_display_clk_rst_en PASS ram_2b1B PASS xprop_or_2u2_2 PASS xprop_and_2u2_2 PASS ram_1b1B PASS always_display_star_en PASS uut_00049.ys PASS init_9b1B_zeros_zero PASS init_9b1B_zeros_any PASS uut_00051.ys PASS uut_00050.ys PASS xprop_or_1u1_1 PASS empty.aag PASS roundtrip_dec_unsigned PASS uut_00032.ys PASS false.aag PASS xprop_xor_2u2_2 PASS xprop_xor_1s1_2 PASS uut_00033.ys PASS uut_00052.ys PASS idranges.lib PASS code_hdl_models_pri_encoder_using_assign.v PASS issue3498_bad.lib PASS bram_01_00 PASS test_simulation_shifter.v PASS uut_00053.ys PASS halfadder.aag PASS xprop_xnor_1s1_2 PASS xprop_xnor_1u1_1 PASS roundtrip_dec_signed PASS constpower.v PASS uut_00054.ys PASS defvalue.sv PASS add_sub.ys PASS uut_00055.ys PASS bram_01_04 make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' PASS inverter.aag make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/fabulous' PASS uut_00029.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' PASS uut_00036.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' PASS xprop_xnor_2u2_2 make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' PASS notcnt1.aag PASS non-ascii.lib PASS uut_00056.ys PASS roundtrip_hex_unsigned PASS uut_00037.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' PASS uut_00057.ys PASS uut_00058.ys PASS notcnt1e.aag PASS roundtrip_hex_signed PASS add_sub.ys PASS uut_00022.ys PASS asgn_binop.sv PASS bug1630.ys PASS xprop_add_5u3_3 PASS uut_00059.ys PASS normal.lib make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' PASS uut_00060.ys PASS uut_00061.ys PASS init_9b1B_val_zero PASS defvalue.sv PASS uut_00062.ys PASS roundtrip_oct_unsigned PASS uut_00031.ys PASS or_.aag PASS uut_00015.ys PASS async_big PASS uut_00063.ys PASS const_func_shadow.v PASS carry.ys PASS code_hdl_models_tff_async_reset.v PASS uut_00064.ys PASS counter.ys PASS uut_00034.ys PASS dff_different_styles.v PASS code_hdl_models_serial_crc.v PASS roundtrip_oct_signed PASS processdefs.lib PASS symbols.aag PASS uut_00066.ys PASS sync_big_lut PASS const_func_shadow.v PASS uut_00065.ys PASS uut_00067.ys PASS adffs.ys PASS complexflop.ys PASS dff_init.v PASS bram_02_01 PASS bram_02_04 PASS uut_00068.ys PASS roundtrip_bin_unsigned PASS bram_02_03 PASS add_sub.ys PASS uut_00038.ys PASS toggle-re.aag PASS uut_00069.ys PASS uut_00039.ys PASS uut_00040.ys PASS semicolmissing.lib PASS bram_02_00 PASS unquoted.lib PASS semicolextra.lib PASS retention.lib PASS add_sub.ys PASS xprop_add_5s3_3 PASS roundtrip_bin_signed PASS dffs.ys PASS toggle.aag PASS counter.ys PASS uut_00070.ys PASS libcache.ys PASS uut_00071.ys PASS options_test.ys PASS uut_00013.ys PASS io.ys PASS uut_00072.ys PASS true.aag PASS read_liberty.ys PASS uut_00073.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/liberty' ...passed tests in ./liberty PASS test_simulation_techmap_tech.v PASS counter.ys PASS init_9b1B_val_any PASS uut_00074.ys PASS neg.ys PASS aigmap make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/aiger' ...passed tests in ./aiger PASS add_sub.ys PASS xprop_sub_5u3_3 PASS asgn_binop.sv PASS abc9.v PASS init_9b1B_val_no_undef PASS uut_00075.ys PASS customisation.ys PASS init_13b2B_val_any PASS blockram.ys PASS lutram.ys PASS uut_00009.ys PASS uut_00076.ys PASS init_18b2B_val_any PASS muldiv_c.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/peepopt' ...passed tests in ./peepopt PASS xprop_sub_5s3_3 PASS uut_00077.ys PASS counter.ys PASS add_sub.ys PASS forgen01.v PASS uut_00078.ys PASS add_sub.ys PASS bram_03_02 PASS uut_00079.ys PASS logic.ys PASS bug5688.ys PASS bug1459.ys PASS init_18b2B_val_no_undef make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/microchip' PASS bug1598.ys PASS uut_00080.ys PASS bug1460.ys PASS fsm.ys PASS init_4b1B_x_none PASS bram_03_01 PASS uut_00081.ys PASS uut_00041.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/logTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/logTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS fiedler-cooley.v PASS uut_00082.ys PASS adffs.ys PASS uut_00083.ys PASS constmuldivmod.v PASS uut_00019.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' PASS test_intermout.v make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/hana' ...passed tests in ./hana PASS bug2409.ys PASS uut_00084.ys PASS uut_00085.ys PASS bram_01_02 PASS uut_00014.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' PASS uut_00020.ys PASS adffs.ys PASS logic.ys PASS uut_00086.ys PASS init_4b1B_x_any PASS init_4b1B_x_zero PASS bram_01_03 PASS uut_00087.ys PASS bug1480.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' PASS bug1836.ys PASS clock_a4_wANYrANYsFalse make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' PASS bug1462.ys PASS uut_00088.ys PASS uut_00007.ys PASS bug1598.ys PASS latches.ys PASS init_4b1B_x_no_undef PASS uut_00089.ys PASS counter.ys PASS uut_00042.ys PASS uut_00090.ys PASS uut_00018.ys PASS uut_00091.ys PASS counter.ys PASS uut_00092.ys PASS logic.ys PASS add_sub.ys PASS fsm.ys PASS compare.ys PASS uut_00011.ys PASS bram_03_00 PASS dffs.ys PASS uut_00093.ys PASS uut_00035.ys PASS uut_00094.ys PASS bug2731.ys PASS xprop_mul_5u3_3 PASS dffs.ys PASS uut_00095.ys PASS regfile.ys PASS uut_00096.ys PASS uut_00097.ys PASS uut_00098.ys PASS uut_00099.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/share' PASS counter.ys ...passed tests in ./share PASS forgen02.v PASS fsm.ys PASS clock_a4_wANYrPOSsFalse PASS uut_00043.ys PASS clock_a4_wANYrNEGsFalse g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/techmap/libparseTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/techmap/libparseTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS tribuf.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/fabulous' ...passed tests in ./arch/fabulous g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/hashTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/hashTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS constmuldivmod.v PASS uut_00017.ys PASS add_sub.ys PASS counter.ys PASS code_hdl_models_tff_sync_reset.v PASS xprop_mul_5s3_3 PASS add_sub.ys PASS display_lm PASS fsm.ys PASS xprop_div_5u3_3 PASS dffs.ys PASS mux.ys PASS bram_03_04 PASS uut_00016.ys PASS clock_a4_wNEGrANYsFalse PASS clock_a4_wNEGrPOSsFalse PASS uut_00044.ys PASS clock_a4_wNEGrNEGsFalse PASS shifter.ys PASS adffs.ys PASS cxxrtl_always_comb PASS clock_a4_wPOSrNEGsFalse PASS clock_a4_wPOSrANYsFalse PASS forgen01.v PASS dff_different_styles.v PASS tribuf.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' ...passed tests in ./arch/efinix PASS uut_00030.ys PASS clock_a4_wPOSrPOSsFalse PASS dffs.ys PASS fiedler-cooley.v PASS adffs.ys PASS logic.ys PASS forgen02.v PASS uut_00045.ys PASS clock_a4_wANYrANYsTrue PASS uut_00047.ys PASS dffs.ys PASS dffs.ys PASS uut_00046.ys PASS clock_a4_wNEGrPOSsTrue PASS counter.ys PASS uut_00048.ys PASS dff_init.v PASS uut_00049.ys PASS tribuf.ys PASS uut_00050.ys PASS bram_04_00 PASS init-error.ys PASS dffs.ys PASS fsm.ys PASS adffs.ys PASS fsm.ys PASS clock_a4_wNEGrNEGsTrue PASS uut_00051.ys PASS uut_00052.ys PASS clock_a4_wPOSrPOSsTrue PASS clock_a4_wPOSrNEGsTrue PASS uut_00053.ys PASS uut_00054.ys PASS unmixed PASS uut_00055.ys PASS mixed_9_18 PASS xprop_div_5s3_3 PASS asym_ram_sdp.ys PASS shifter.ys PASS uut_00056.ys PASS mixed_18_9 PASS latches.ys PASS async_big_block PASS uut_00057.ys PASS uut_00058.ys PASS mixed_4_2 PASS forloops.v PASS mixed_36_9 PASS uut_00059.ys PASS tdp PASS uut_00060.ys PASS fsm.ys PASS logic.ys PASS uut_00061.ys PASS uut_00062.ys PASS uut_00063.ys PASS bug1597.ys PASS bug1598.ys PASS uut_00064.ys PASS mux.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' ...passed tests in ./arch/quicklogic/pp3 PASS bug1626.ys PASS uut_00065.ys PASS bram_04_01 PASS uut_00023.ys PASS uut_00066.ys PASS sync_2clk PASS mux.ys PASS mul.ys PASS uut_00067.ys PASS uut_00068.ys PASS shifter.ys PASS uut_00069.ys PASS uut_00070.ys PASS xprop_mod_5u3_3 PASS uut_00071.ys PASS uut_00072.ys PASS counter.ys PASS uut_00074.ys PASS sync_shared PASS uut_00073.ys PASS add_sub.ys PASS blockram.ys PASS logic.ys PASS tribuf.ys PASS uut_00075.ys PASS bram_04_02 PASS fsm.ys PASS dynslice.v PASS mul.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/rtlilStringTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/rtlilStringTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS adffs.ys PASS func_recurse.v PASS sync_trans_old_none PASS sync_trans_old_new make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bind' PASS sync_trans_old_old make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' PASS fsm.v PASS counter.ys PASS basic.ys PASS cell_list.ys PASS hier.ys PASS sync_trans_new_old PASS sync_2clk_shared PASS inst_list.ys PASS dsp_abc9.ys PASS param.ys PASS code_hdl_models_cam.v PASS func_block.v PASS toplevel.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bind' ...passed tests in ./bind PASS logic.ys PASS ice40_dsp.ys PASS opt_lut_ins.ys PASS failures.ys PASS sync_trans_new_new PASS bram_04_03 make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bram' ...passed tests in ./bram PASS case_large.v PASS uut_00024.ys PASS bug2061.ys PASS sync_trans_new_none PASS sp_nc_none PASS sp_new_none PASS forloops.v PASS counter.ys PASS lutram.ys PASS dffs.ys PASS genblk_collide.v PASS uut_00021.ys PASS logic.ys PASS xprop_mod_5s3_3 PASS latches.ys PASS lutram.ys PASS genblk_dive.v PASS code_hdl_models_uart.v PASS fsm.v PASS mul_unsigned.ys PASS genblk_order.v PASS sp_old_none PASS sp_nc_nc PASS code_hdl_models_up_counter.v PASS tribuf.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' ...passed tests in ./arch/intel_alm PASS adffs.ys PASS genblk_port_shadow.v PASS uut_00078.ys PASS uut_00079.ys PASS uut_00080.ys PASS func_width_scope.v PASS sp_new_nc PASS uut_00077.ys PASS sp_old_nc PASS ice40_dsp_const.ys PASS sp_nc_new PASS fsm.ys PASS code_hdl_models_up_counter_load.v PASS latches.ys PASS mux.ys PASS uut_00025.ys PASS mux.ys PASS cxxrtl_always_full PASS shifter.ys PASS always_full_equiv make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/fmt' ...passed tests in ./fmt g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/bitpatternTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/bitpatternTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS xprop_divfloor_5u3_3 PASS fsm.ys PASS sp_new_new PASS init.ys PASS sp_new_old PASS sp_nc_old PASS sp_old_new PASS uut_00081.ys PASS dpram.ys PASS uut_00082.ys PASS proc_constraints.ys PASS tribuf.ys PASS sp_old_old g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/sigspecExtractTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/sigspecExtractTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS fsm.ys PASS sp_nc_new_only PASS xprop_divfloor_5s3_3 PASS latches.ys PASS code_hdl_models_up_down_counter.v PASS dffs.ys PASS uut_00026.ys PASS latches_abc9.ys PASS uut_00083.ys PASS sp_old_new_only PASS sp_new_new_only PASS bug3670.ys PASS logic.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt' PASS alumacc.ys PASS mux.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' PASS bug1525.ys ...passed tests in ./arch/anlogic PASS shifter.ys PASS bug1758.ys PASS bug1854.ys PASS sp_nc_new_only_be PASS bug2010.ys PASS code_tidbits_blocking.v PASS bug2221.ys PASS logic.ys PASS code_tidbits_asyn_reset.v PASS func_block.v PASS bug2311.ys PASS bug2318.ys PASS bug2623.ys PASS bug2765.ys PASS uut_00022.ys PASS hierarchy.v PASS dffs.ys PASS sp_new_new_only_be PASS bug2824.ys PASS code_specman_switch_fabric.v PASS graphtest.v PASS bug2766.ys PASS mul.ys PASS bug2920.ys PASS uut_00084.ys PASS bug3047.ys PASS sp_old_new_only_be PASS bug3117.ys PASS bug3848.ys PASS bug3867.ys PASS bug4413.ys PASS counter.ys PASS bug4610.ys PASS xprop_modfloor_5u3_3 PASS bug5164.ys PASS bug5398.ys PASS hierdefparam.v PASS shifter.ys PASS raise_error.ys PASS memory_bmux2rom.ys PASS logic.ys PASS ice40_wrapcarry.ys PASS sp_nc_new_be PASS shifter.ys PASS code_tidbits_fsm_using_always.v PASS dff_opt.ys PASS memory_dff_trans.ys PASS i2c_master_tests.v PASS fsm.ys PASS fsm.ys PASS uut_00085.ys PASS latches.ys PASS sp_new_new_be make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sat' PASS opt_clean_init.ys PASS memory_map_offset.ys PASS asserts.ys PASS macc.ys PASS asserts_seq.ys PASS bug2595.ys PASS sp_old_new_be PASS opt_balance_tree.ys PASS opt_clean_init_const.ys PASS ifdef_1.v PASS code_tidbits_fsm_using_function.v PASS opt_clean_mem.ys PASS opt_clean_standalone_wires.ys PASS ifdef_2.v PASS uut_00086.ys PASS opt_dff-simplify.ys PASS dynslice.v PASS func_recurse.v PASS sp_nc_old_be PASS uut_00087.ys PASS opt_dff_arst.ys PASS uut_00088.ys PASS opt_dff_clk.ys PASS xprop_modfloor_5s3_3 PASS counters-repeat.ys PASS sp_new_old_be PASS code_tidbits_fsm_using_single_always.v PASS attributes_test.ys PASS xprop_lt_5u3_2 PASS adffs.ys PASS opt_dff_dffmux.ys PASS tribuf.ys PASS opt_dff_const.ys PASS sp_old_old_be g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/opt/optDffFindComplementaryPatternTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/opt/optDffFindComplementaryPatternTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS xprop_lt_5s3_2 g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/ioTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/ioTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS mux.ys PASS t_mem0.ys PASS mul.ys PASS code_tidbits_nonblocking.v PASS counters.ys PASS sp_nc_nc_be PASS dff.ys PASS sp_new_nc_be PASS xprop_le_5u3_2 PASS sp_old_nc_be PASS opt_dff_en.ys PASS logic.ys PASS opt_dff_qd.ys PASS ice40_opt.ys PASS code_tidbits_reg_seq_example.v PASS code_tidbits_reg_combo_example.v PASS expose_dff.ys PASS sp_nc_auto PASS mod_constraints.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' ...passed tests in ./bugpoint PASS opt_dff_mux.ys PASS sp_new_auto PASS code_tidbits_syn_reset.v PASS uut_00031.ys PASS bug1462.ys PASS bug1460.ys PASS bug1480.ys PASS uut_00089.ys PASS memory.ys PASS uut_00090.ys PASS sp_old_auto PASS uut_00091.ys PASS opt_dff_srst.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/modindexTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/modindexTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS xprop_le_5s3_2 PASS mul_gw1n.ys PASS opt_expr_alu.ys PASS div.ys PASS opt_expr.ys PASS code_tidbits_wire_example.v PASS uut_00027.ys PASS fminit_noexpand.ys PASS sp_nc_auto_be PASS uut_00028.ys PASS t_mem1.ys PASS code_verilog_tutorial_addbit.v PASS sp_new_auto_be PASS code_verilog_tutorial_always_example.v PASS sp_old_auto_be PASS func_width_scope.v PASS mux.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/cellTypesTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/cellTypesTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS adffs.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/sigspecRemove2Test /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/sigspecRemove2Test.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS opt_dff_sr.ys PASS shifter.ys PASS opt_expr_and.ys PASS xprop_eq_5u3_2 PASS opt_expr_cmp.ys PASS code_verilog_tutorial_bus_con.v PASS dpram.ys PASS sp_init_x_x PASS bug1605.ys PASS opt_expr_combined_assign.ys PASS mul_gw2a.ys PASS opt_expr_constconn.ys PASS opt_expr_consumex.ys PASS sp_init_x_x_re PASS sp_init_0_x PASS opt_expr_mux_undef.ys PASS sp_init_x_x_ce PASS opt_expr_or.ys PASS code_verilog_tutorial_counter.v PASS dsp_fastfir.ys PASS uut_00092.ys PASS uut_00035.ys PASS code_verilog_tutorial_comment.v PASS code_verilog_tutorial_counter_tb.v PASS opt_expr_more.ys PASS fminit_seq_width.ys PASS case_large.v PASS opt_expr_shift.ys PASS opt_expr_shr_int_max.ys PASS opt_expr_xnor.ys PASS sp_init_0_x_re PASS uut_00036.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sdc' PASS genblk_collide.v PASS alu_sub.ys PASS opt_expr_xor.ys PASS side-effects.sh PASS unknown-getter.sh make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sdc' ...passed tests in ./sdc PASS counter.ys PASS implicit_ports.sv PASS code_verilog_tutorial_d_ff.v PASS genblk_dive.v PASS xprop_eq_5s3_2 PASS opt_lut_elim.ys PASS code_verilog_tutorial_decoder_always.v PASS logic.ys PASS code_verilog_tutorial_decoder.v PASS sp_init_0_0 PASS uut_00030.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sim' PASS assume_x_first_step.ys PASS sim_adff.ys PASS opt_lut_ins.ys PASS latches.ys PASS code_verilog_tutorial_escape_id.v PASS sim_adffe.ys PASS opt_lut_ins.ys PASS initval.ys PASS sim_adlatch.ys PASS uut_00033.ys PASS lutram.ys PASS genblk_order.v PASS sim_aldff.ys PASS genblk_port_shadow.v PASS sp_init_0_0_re PASS sim_aldffe.ys PASS uut_00029.ys PASS graphtest.v PASS code_verilog_tutorial_explicit.v PASS sim_cycles.ys PASS grom.ys g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/threadingTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/threadingTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS sim_dff.ys PASS t_mem2.ys PASS sim_dffe.ys PASS opt_lut_port.ys PASS sim_dffsr.ys PASS mux.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' PASS sim_dlatch.ys PASS array_assign_flat_multidim_pattern.ys PASS sim_dlatchsr.ys PASS localparam_attr.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' PASS enum_simple.ys PASS local_loop_var.sv PASS xprop_ne_5u3_2 PASS sp_init_0_any PASS sim_sdff.ys PASS logic_rom.ys PASS sim_sdffce.ys PASS lesser_size_cast.sv PASS sim_sdffe.ys PASS multirange_subarray_access.ys PASS code_verilog_tutorial_first_counter.v PASS vcd_var_reference_whitespace.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sim' ...passed tests in ./sim PASS code_verilog_tutorial_first_counter_tb.v PASS static_cast_negative.ys PASS abc9-nonbox-loop-with-box.ys PASS loop_var_shadow.v PASS reduce.ys PASS static_cast_nonconst.ys PASS loop_prefix_case.v PASS static_cast_verilog.ys PASS tribuf.ys PASS static_cast_zero.ys PASS uut_00032.ys PASS dffs.ys PASS bug1598.ys PASS code_verilog_tutorial_fsm_full_tb.v PASS sp_init_0_any_re PASS add_sub.ys PASS typedef_initial_and_assign.ys PASS uut_00093.ys PASS uut_00094.ys PASS uut_00096.ys PASS uut_00095.ys PASS struct_dynamic_range.ys PASS hierarchy.v PASS typedef_memory_2.ys PASS dsp.ys PASS typedef_memory.ys PASS tribuf.ys PASS typedef_struct_global.ys PASS rom.ys PASS typedef_struct_port.ys PASS abc_state.ys PASS array_assign.sv PASS abc_temp_dir_sanitization.ys PASS multirange_array.sv PASS code_verilog_tutorial_flip_flop.v PASS add_sub.ys PASS static_cast_simple.sv PASS sp_init_v_x PASS uut_00097.ys PASS struct_array.sv PASS lutram.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' ...passed tests in ./arch/machxo2 PASS struct_simple.sv PASS struct_sizebits.sv PASS code_verilog_tutorial_fsm_full.v PASS opt_mem_priority.ys PASS typedef_package.sv PASS typedef_param.sv PASS uut_00034.ys PASS latches.ys PASS typedef_scopes.sv PASS sp_init_v_x_re PASS sp_init_v_0_re PASS i2c_master_tests.v PASS sp_init_v_0 PASS typedef_simple.sv PASS opt_merge_init.ys PASS opt_merge_basic.ys PASS xprop_ne_5s3_2 PASS typedef_struct.sv PASS union_simple.sv make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' PASS clk2fflogic.ys ...passed tests in ./svtypes PASS blockram.ys PASS opt_lut.ys PASS opt_merge_keep.ys PASS xprop_eqx_5s3_2 PASS code_verilog_tutorial_if_else.v PASS code_verilog_tutorial_good_code.v PASS opt_merge_properties.ys PASS generate.v PASS sp_init_v_any PASS sp_init_v_any_re PASS sp_arst_x_x_re PASS sp_arst_x_x g++ -L/home/buildozer/aports/testing/yosys/src -Wl,-rpath=/home/buildozer/aports/testing/yosys/src -rdynamic -L/usr/lib -o /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/rtlilTest /home/buildozer/aports/testing/yosys/src/tests/unit/objtest/kernel/rtlilTest.o -lstdc++ -lm -lrt -ldl -lm -lreadline -L/usr/lib/../lib -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -lpthread \ -lgtest -lgmock -lgtest_main -lyosys -pthread PASS loops.v PASS hierdefparam.v PASS sim_counter.ys PASS sp_arst_0_x PASS xprop_eqx_5u3_2 PASS sp_arst_0_x_re PASS adff2dff.ys Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/techmap/libparseTest PASS sp_arst_0_0_re PASS macro_arg_spaces.sv PASS sp_arst_0_0 PASS uut_00098.ys Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from TechmapLibparseTest [ RUN ] TechmapLibparseTest.LibertyExpressionSpace [ OK ] TechmapLibparseTest.LibertyExpressionSpace (0 ms) [----------] 1 test from TechmapLibparseTest (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test suite ran. (0 ms total) [ PASSED ] 1 test. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/logTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from KernelLogTest [ RUN ] KernelLogTest.logvValidValues [ OK ] KernelLogTest.logvValidValues (0 ms) [----------] 1 test from KernelLogTest (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test suite ran. (0 ms total) [ PASSED ] 1 test. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/rtlilTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 38 tests from 2 test suites. [----------] Global test environment set-up. [----------] 26 tests from KernelRtlilTest [ RUN ] KernelRtlilTest.ConstAssignCompare [ OK ] KernelRtlilTest.ConstAssignCompare (0 ms) [ RUN ] KernelRtlilTest.ConstStr [ OK ] KernelRtlilTest.ConstStr (0 ms) [ RUN ] KernelRtlilTest.ConstConstIteratorWorks [ OK ] KernelRtlilTest.ConstConstIteratorWorks (0 ms) [ RUN ] KernelRtlilTest.ConstConstIteratorPreincrement [ OK ] KernelRtlilTest.ConstConstIteratorPreincrement (0 ms) [ RUN ] KernelRtlilTest.ConstConstIteratorPostincrement [ OK ] KernelRtlilTest.ConstConstIteratorPostincrement (0 ms) [ RUN ] KernelRtlilTest.ConstIteratorWorks [ OK ] KernelRtlilTest.ConstIteratorWorks (0 ms) [ RUN ] KernelRtlilTest.ConstIteratorPreincrement [ OK ] KernelRtlilTest.ConstIteratorPreincrement (0 ms) [ RUN ] KernelRtlilTest.ConstIteratorPostincrement [ OK ] KernelRtlilTest.ConstIteratorPostincrement (0 ms) [ RUN ] KernelRtlilTest.ConstIteratorWriteWorks [ OK ] KernelRtlilTest.ConstIteratorWriteWorks (0 ms) [ RUN ] KernelRtlilTest.ConstBuilder [ OK ] KernelRtlilTest.ConstBuilder (0 ms) [ RUN ] KernelRtlilTest.ConstSet [ OK ] KernelRtlilTest.ConstSet (0 ms) [ RUN ] KernelRtlilTest.ConstResize [ OK ] KernelRtlilTest.ConstResize (0 ms) [ RUN ] KernelRtlilTest.ConstEqualStr [ OK ] KernelRtlilTest.ConstEqualStr (0 ms) [ RUN ] KernelRtlilTest.ConstEqualBits [ OK ] KernelRtlilTest.ConstEqualBits (0 ms) [ RUN ] KernelRtlilTest.ConstEqualStrBits [ OK ] KernelRtlilTest.ConstEqualStrBits (0 ms) [ RUN ] KernelRtlilTest.ConstEqualHashStrBits [ OK ] KernelRtlilTest.ConstEqualHashStrBits (0 ms) [ RUN ] KernelRtlilTest.ConstIsFullyZero [ OK ] KernelRtlilTest.ConstIsFullyZero (0 ms) [ RUN ] KernelRtlilTest.ConstIsFullyOnes [ OK ] KernelRtlilTest.ConstIsFullyOnes (0 ms) [ RUN ] KernelRtlilTest.ConstIsFullyDef [ OK ] KernelRtlilTest.ConstIsFullyDef (0 ms) [ RUN ] KernelRtlilTest.ConstIsFullyUndef [ OK ] KernelRtlilTest.ConstIsFullyUndef (0 ms) [ RUN ] KernelRtlilTest.ConstIsFullyUndefXOnly [ OK ] KernelRtlilTest.ConstIsFullyUndefXOnly (0 ms) [ RUN ] KernelRtlilTest.ConstIsOnehot [ OK ] KernelRtlilTest.ConstIsOnehot (0 ms) [ RUN ] KernelRtlilTest.OwningIdString [ OK ] KernelRtlilTest.OwningIdString (0 ms) [ RUN ] KernelRtlilTest.LookupAutoidxId [ OK ] KernelRtlilTest.LookupAutoidxId (0 ms) [ RUN ] KernelRtlilTest.NewIdBeginsWith [ OK ] KernelRtlilTest.NewIdBeginsWith (0 ms) [ RUN ] KernelRtlilTest.NewIdIndexing [ OK ] KernelRtlilTest.NewIdIndexing (0 ms) [----------] 26 tests from KernelRtlilTest (1 ms total) [----------] 12 tests from WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__0__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__0__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__0__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__0__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__4__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__4__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__4__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__4__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false___4__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false___4__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true___4__10_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true___4__10_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__0__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__0__1_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__0__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__0__1_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__4__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false__4__1_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__4__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true__4__1_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false___4__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_false___4__1_ (0 ms) [ RUN ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true___4__1_ [ OK ] WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest.WireRtlVsHdlIndexConversion/_true___4__1_ (0 ms) [----------] 12 tests from WireRtlVsHdlIndexConversionInstance/WireRtlVsHdlIndexConversionTest (0 ms total) [----------] Global test environment tear-down [==========] 38 tests from 2 test suites ran. (1 ms total) [ PASSED ] 38 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/ioTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 15 tests from 1 test suite. [----------] Global test environment set-up. [----------] 15 tests from KernelStringfTest [ RUN ] KernelStringfTest.integerTruncation [ OK ] KernelStringfTest.integerTruncation (1 ms) [ RUN ] KernelStringfTest.charFormat [ OK ] KernelStringfTest.charFormat (0 ms) [ RUN ] KernelStringfTest.floatFormat [ OK ] KernelStringfTest.floatFormat (0 ms) [ RUN ] KernelStringfTest.intToFloat [ OK ] KernelStringfTest.intToFloat (0 ms) [ RUN ] KernelStringfTest.floatToInt [ OK ] KernelStringfTest.floatToInt (0 ms) [ RUN ] KernelStringfTest.stringParam [ OK ] KernelStringfTest.stringParam (0 ms) [ RUN ] KernelStringfTest.stringViewParam [ OK ] KernelStringfTest.stringViewParam (0 ms) [ RUN ] KernelStringfTest.idStringParam [ OK ] KernelStringfTest.idStringParam (0 ms) [ RUN ] KernelStringfTest.escapePercent [ OK ] KernelStringfTest.escapePercent (0 ms) [ RUN ] KernelStringfTest.trailingPercent [ OK ] KernelStringfTest.trailingPercent (0 ms) [ RUN ] KernelStringfTest.dynamicWidth [ OK ] KernelStringfTest.dynamicWidth (0 ms) [ RUN ] KernelStringfTest.dynamicPrecision [ OK ] KernelStringfTest.dynamicPrecision (0 ms) [ RUN ] KernelStringfTest.dynamicWidthAndPrecision [ OK ] KernelStringfTest.dynamicWidthAndPrecision (0 ms) [ RUN ] KernelStringfTest.dynamicPrecisionInt [ OK ] KernelStringfTest.dynamicPrecisionInt (0 ms) [ RUN ] KernelStringfTest.dynamicWidthAndPrecisionInt [ OK ] KernelStringfTest.dynamicWidthAndPrecisionInt (0 ms) [----------] 15 tests from KernelStringfTest (1 ms total) [----------] Global test environment tear-down [==========] 15 tests from 1 test suite ran. (1 ms total) [ PASSED ] 15 tests. PASS lutram.ys Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/modindexTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 2 tests from 2 test suites. [----------] Global test environment set-up. [----------] 1 test from ModIndexSwapTest [ RUN ] ModIndexSwapTest.has [ OK ] ModIndexSwapTest.has (0 ms) [----------] 1 test from ModIndexSwapTest (0 ms total) [----------] 1 test from ModIndexDeleteTest [ RUN ] ModIndexDeleteTest.has --- ModIndex Dump --- BIT $w: PORT: $not.A[0] ($_NOT_) BIT $o: PRIMARY OUTPUT PORT: $not.Y[0] ($_NOT_) [ OK ] ModIndexDeleteTest.has (0 ms) [----------] 1 test from ModIndexDeleteTest (0 ms total) [----------] Global test environment tear-down [==========] 2 tests from 2 test suites ran. (0 ms total) [ PASSED ] 2 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/cellTypesTest PASS uut_00099.ys PASS code_verilog_tutorial_multiply.v Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from CellTypesTest [ RUN ] CellTypesTest.basic PASS opt_reduce_andor.ys PASS autopurge.ys Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/sigspecRemove2Test Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 12 tests from 1 test suite. [----------] Global test environment set-up. [----------] 12 tests from SigSpecRepTest [ RUN ] SigSpecRepTest.WithSigSpecPattern [ OK ] SigSpecRepTest.WithSigSpecPattern (0 ms) [ RUN ] SigSpecRepTest.WithPoolPattern [ OK ] SigSpecRepTest.WithPoolPattern (0 ms) [ RUN ] SigSpecRepTest.WithSetPattern [ OK ] SigSpecRepTest.WithSetPattern (0 ms) [ RUN ] SigSpecRepTest.ManyElements [ OK ] SigSpecRepTest.ManyElements (0 ms) [ RUN ] SigSpecRepTest.VeryLargeScalingTest PASS code_verilog_tutorial_n_out_primitive.v PASS aigmap.ys PASS code_verilog_tutorial_task_global.v PASS code_verilog_tutorial_simple_function.v PASS code_verilog_tutorial_parallel_if.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/various' PASS code_verilog_tutorial_simple_if.v PASS opt_pow.ys PASS abstract_initstates.ys PASS abstract_init.ys [ OK ] SigSpecRepTest.VeryLargeScalingTest (120 ms) [ RUN ] SigSpecRepTest.MultipleSequentialRemovals [ OK ] SigSpecRepTest.MultipleSequentialRemovals (14 ms) [ RUN ] SigSpecRepTest.PoolOverloadLargeDataset PASS code_verilog_tutorial_mux_21.v PASS xprop_nex_5u3_2 PASS opt_reduce_bmux.ys PASS sp_arst_0_any PASS abstract_state.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/rtlil' [ OK ] SigSpecRepTest.PoolOverloadLargeDataset (92 ms) [ RUN ] SigSpecRepTest.SetOverloadLargeDataset PASS lutram.ys PASS code_verilog_tutorial_parity.v PASS bug5424.ys PASS macro_arg_surrounding_spaces.v make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' PASS ifdef_1.v PASS absurd_width.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arith_tree' PASS sp_arst_0_any_re PASS absurd_width_const.ys PASS roundtrip-design.sh [ OK ] SigSpecRepTest.SetOverloadLargeDataset (94 ms) [ RUN ] SigSpecRepTest.RemoveAlmostAllElements [ OK ] SigSpecRepTest.RemoveAlmostAllElements (12 ms) [ RUN ] SigSpecRepTest.EmptyPattern [ OK ] SigSpecRepTest.EmptyPattern (0 ms) [ RUN ] SigSpecRepTest.NullWireBitsStay [ OK ] SigSpecRepTest.NullWireBitsStay (0 ms) [ RUN ] SigSpecRepTest.PartialBitRemoval [ OK ] SigSpecRepTest.PartialBitRemoval (0 ms) [----------] 12 tests from SigSpecRepTest (335 ms total) [----------] Global test environment tear-down [==========] 12 tests from 1 test suite ran. (335 ms total) [ PASSED ] 12 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/bitpatternTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from BitpatternTest [ RUN ] BitpatternTest.has [ OK ] BitpatternTest.has (0 ms) [----------] 1 test from BitpatternTest (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test suite ran. (0 ms total) [ PASSED ] 1 test. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/sigspecExtractTest PASS always_comb_latch_1.ys Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 1 test from 1 test suite. [----------] Global test environment set-up. [----------] 1 test from SigSpecRepTest [ RUN ] SigSpecRepTest.Extract [ OK ] SigSpecRepTest.Extract (0 ms) [----------] 1 test from SigSpecRepTest (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test suite ran. (0 ms total) [ PASSED ] 1 test. PASS arith_tree_add_chains.ys PASS uut_00040.ys Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/rtlilStringTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 4 tests from 1 test suite. [----------] Global test environment set-up. [----------] 4 tests from RtlilStrTest [ RUN ] RtlilStrTest.DesignToString [ OK ] RtlilStrTest.DesignToString (0 ms) [ RUN ] RtlilStrTest.ModuleToString [ OK ] RtlilStrTest.ModuleToString (0 ms) [ RUN ] RtlilStrTest.WireToString [ OK ] RtlilStrTest.WireToString (0 ms) [ RUN ] RtlilStrTest.CellToString [ OK ] RtlilStrTest.CellToString (0 ms) [----------] 4 tests from RtlilStrTest (0 ms total) [----------] Global test environment tear-down [==========] 4 tests from 1 test suite ran. (0 ms total) [ PASSED ] 4 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/threadingTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 25 tests from 1 test suite. [----------] Global test environment set-up. [----------] 25 tests from ThreadingTest [ RUN ] ThreadingTest.ParallelDispatchThreadPoolCreate [ OK ] ThreadingTest.ParallelDispatchThreadPoolCreate (0 ms) [ RUN ] ThreadingTest.ParallelDispatchThreadPoolRunSimple [ OK ] ThreadingTest.ParallelDispatchThreadPoolRunSimple (0 ms) [ RUN ] ThreadingTest.ParallelDispatchThreadPoolRunMultiple PASS always_comb_latch_2.ys [ OK ] ThreadingTest.ParallelDispatchThreadPoolRunMultiple (0 ms) [ RUN ] ThreadingTest.ParallelDispatchThreadPoolRunCtxThreadNums [ OK ] ThreadingTest.ParallelDispatchThreadPoolRunCtxThreadNums (0 ms) [ RUN ] ThreadingTest.ParallelDispatchThreadPoolItemRange [ OK ] ThreadingTest.ParallelDispatchThreadPoolItemRange (0 ms) [ RUN ] ThreadingTest.ParallelDispatchThreadPoolSubpool [ OK ] ThreadingTest.ParallelDispatchThreadPoolSubpool (0 ms) [ RUN ] ThreadingTest.IntRangeIteration [ OK ] ThreadingTest.IntRangeIteration (0 ms) [ RUN ] ThreadingTest.IntRangeEmpty [ OK ] ThreadingTest.IntRangeEmpty (0 ms) [ RUN ] ThreadingTest.ItemRangeForWorker [ OK ] ThreadingTest.ItemRangeForWorker (0 ms) [ RUN ] ThreadingTest.ItemRangeForWorkerZeroThreads [ OK ] ThreadingTest.ItemRangeForWorkerZeroThreads (0 ms) [ RUN ] ThreadingTest.ShardedVectorBasic [ OK ] ThreadingTest.ShardedVectorBasic (0 ms) [ RUN ] ThreadingTest.MonotonicFlagBasic [ OK ] ThreadingTest.MonotonicFlagBasic (0 ms) [ RUN ] ThreadingTest.MonotonicFlagSetAndReturnOld [ OK ] ThreadingTest.MonotonicFlagSetAndReturnOld (0 ms) [ RUN ] ThreadingTest.ConcurrentQueueBasic [ OK ] ThreadingTest.ConcurrentQueueBasic (0 ms) [ RUN ] ThreadingTest.ConcurrentQueueTryPopEmpty [ OK ] ThreadingTest.ConcurrentQueueTryPopEmpty (0 ms) [ RUN ] ThreadingTest.ConcurrentQueueClose [ OK ] ThreadingTest.ConcurrentQueueClose (0 ms) [ RUN ] ThreadingTest.ThreadPoolCreate [ OK ] ThreadingTest.ThreadPoolCreate (0 ms) [ RUN ] ThreadingTest.ThreadPoolMultipleThreads [ OK ] ThreadingTest.ThreadPoolMultipleThreads (0 ms) [ RUN ] ThreadingTest.ShardedHashtableBasic [ OK ] ThreadingTest.ShardedHashtableBasic (0 ms) [ RUN ] ThreadingTest.ShardedHashtableParallelInsert [ OK ] ThreadingTest.ShardedHashtableParallelInsert (0 ms) [ RUN ] ThreadingTest.ShardedHashtableCollision [ OK ] ThreadingTest.ShardedHashtableCollision (0 ms) [ RUN ] ThreadingTest.ShardedHashtableEmpty [ OK ] ThreadingTest.ShardedHashtableEmpty (0 ms) [ RUN ] ThreadingTest.ConcurrentWorkQueueSingleThread [ OK ] ThreadingTest.ConcurrentWorkQueueSingleThread (0 ms) [ RUN ] ThreadingTest.ConcurrentWorkQueueBatching [ OK ] ThreadingTest.ConcurrentWorkQueueBatching (0 ms) [ RUN ] ThreadingTest.ConcurrentWorkQueueParallel [ OK ] ThreadingTest.ConcurrentWorkQueueParallel (0 ms) [----------] 25 tests from ThreadingTest (1 ms total) [----------] Global test environment tear-down [==========] 25 tests from 1 test suite ran. (1 ms total) [ PASSED ] 25 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/kernel/hashTest Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 3 tests from 2 test suites. [----------] Global test environment set-up. [----------] 1 test from CommutativeTest [ RUN ] CommutativeTest.basic [ OK ] CommutativeTest.basic (0 ms) [----------] 1 test from CommutativeTest (0 ms total) [----------] 2 tests from PoolHashTest [ RUN ] PoolHashTest.collisions PASS always_comb_latch_3.ys PASS roundtrip-text.sh make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/rtlil' ...passed tests in ./rtlil PASS always_comb_latch_4.ys PASS sp_arst_0_init_re PASS ifdef_2.v PASS always_comb_nolatch_1.ys PASS bmuxmap_pmux.ys PASS always_comb_nolatch_2.ys PASS sp_arst_0_init PASS always_comb_nolatch_3.ys PASS always_comb_nolatch_4.ys PASS opt_reduce_demux.ys PASS opt_mem_feedback.ys PASS always_comb_nolatch_5.ys PASS always_comb_nolatch_6.ys PASS shifter.ys PASS arith_tree_alu_macc_equiv.ys PASS code_verilog_tutorial_tri_buf.v PASS asgn_expr.ys PASS asgn_expr_not_proc_1.ys pool collisions: 3206 PASS code_verilog_tutorial_v2k_reg.v PASS arith_tree_edge_cases.ys PASS asgn_expr_not_proc_2.ys PASS uram_ar.ys PASS macros.v PASS asgn_expr_not_proc_3.ys PASS matching_end_labels.sv PASS abstract_value.ys [ OK ] PoolHashTest.collisions (408 ms) [ RUN ] PoolHashTest.subset_collisions PASS asgn_expr_not_proc_4.ys PASS opt_rmdff_sat.ys PASS asgn_expr_not_proc_5.ys PASS buf.ys PASS tribuf.ys PASS asgn_expr_not_sv_1.ys PASS arith_tree_idempotent.ys PASS sizebits.ys PASS sp_arst_v_x PASS asgn_expr_not_sv_2.ys PASS splice.ys PASS asgn_expr_not_sv_3.ys PASS share.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sat' ...passed tests in ./sat PASS abc9.ys PASS asgn_expr_not_sv_4.ys PASS uut_00041.ys PASS uram_sr.ys PASS uut_00038.ys PASS assign_to_reg.ys PASS arith_tree_negative.ys PASS atom_type_signedness.ys PASS aiger2.ys PASS arith_tree_equiv.ys PASS automatic_lifetime.ys PASS opt_share_add_sub.ys PASS uut_00076.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' ...passed tests in ./opt_share PASS aiger_dff.ys PASS implicit_ports.sv PASS xprop_nex_5s3_2 PASS arith_tree_sub_chains.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arith_tree' ...passed tests in ./arith_tree PASS block_end_label_only.ys PASS opt_share_bug2334.ys PASS attrib07_func_call.ys PASS opt_share_bug2335.ys PASS attrib05_port_conn.ys PASS opt_share_bug2336.ys PASS block_end_label_wrong.ys PASS autoname.ys PASS block_labels.ys PASS bufnorm.ys PASS blackbox_wb.ys PASS sp_arst_v_x_re PASS bug2037.ys PASS opt_rmdff.ys PASS sp_arst_v_0 PASS box_derive.ys PASS bug2042-sv.ys PASS sp_arst_v_0_re PASS opt_share_bug2538.ys PASS code_verilog_tutorial_which_clock.v PASS bufnorm_opt_clean.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' ...passed tests in ./asicworld PASS bug2042.ys PASS bug1496.ys PASS sp_arst_v_any PASS bug2493.ys PASS bug2183.ys PASS bug4785.ys PASS xprop_ge_5u3_2 PASS bug1531.ys PASS bug5572.ys PASS opt_share_cat.ys PASS bug1614.ys PASS bug656.ys PASS bug1710.ys PASS sp_arst_v_any_re PASS conflict_assert.ys PASS opt_share_cat_multiuser.ys PASS bug1745.ys PASS opt_share_diff_port_widths.ys PASS conflict_cell_memory.ys PASS bug1781.ys PASS bug1876.ys PASS mem2reg_bounds_tern.v PASS bug2014.ys PASS conflict_interface_port.ys PASS opt_share_extend.ys PASS bug3462.ys PASS lesser_size_cast.sv PASS conflict_memory_wire.ys PASS conflict_pwire.ys PASS bug3515.ys PASS sp_arst_v_init PASS memwr_port_connection.sv PASS uut_00043.ys PASS conflict_wire_memory.ys PASS bug4082.ys PASS bug4909.ys PASS bug4865.ys make[2]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/realmath' PASS opt_share_large_pmux_cat.ys PASS bug2321.ys PASS const_arst.ys PASS bug3879.ys PASS const_sr.ys PASS cellarray_array_connections.ys PASS constparser_f.ys PASS uut_00001 pool subset collisions: 92 PASS uut_00000 PASS constparser_f_file.ys PASS constparser_g.ys PASS sp_arst_v_init_re PASS opt_share_large_pmux_cat_multipart.ys PASS sp_arst_e_x PASS delay_mintypmax.ys PASS uut_00002 PASS opt_share_large_pmux_multipart.ys PASS delay_risefall.ys PASS xprop_ge_5s3_2 PASS delay_time_scale.ys PASS module_scope.v [ OK ] PoolHashTest.subset_collisions (1182 ms) [----------] 2 tests from PoolHashTest (1591 ms total) [----------] Global test environment tear-down [==========] 3 tests from 2 test suites ran. (1591 ms total) [ PASSED ] 3 tests. Running /home/buildozer/aports/testing/yosys/src/tests/unit/bintest/opt/optDffFindComplementaryPatternTest PASS opt_share_large_pmux_part.ys Running main() from /home/buildozer/aports/main/gtest/src/googletest-1.17.0/googletest/src/gtest_main.cc [==========] Running 12 tests from 1 test suite. [----------] Global test environment set-up. [----------] 12 tests from FindComplementaryPatternVarTest [ RUN ] FindComplementaryPatternVarTest.EmptyPatterns [ OK ] FindComplementaryPatternVarTest.EmptyPatterns (0 ms) [ RUN ] FindComplementaryPatternVarTest.IdenticalSingleVar [ OK ] FindComplementaryPatternVarTest.IdenticalSingleVar (0 ms) [ RUN ] FindComplementaryPatternVarTest.ComplementarySingleVar [ OK ] FindComplementaryPatternVarTest.ComplementarySingleVar (0 ms) [ RUN ] FindComplementaryPatternVarTest.MissingKeyInRight [ OK ] FindComplementaryPatternVarTest.MissingKeyInRight (0 ms) [ RUN ] FindComplementaryPatternVarTest.TwoVarsOneComplementary [ OK ] FindComplementaryPatternVarTest.TwoVarsOneComplementary (0 ms) [ RUN ] FindComplementaryPatternVarTest.TwoVarsBothComplementary [ OK ] FindComplementaryPatternVarTest.TwoVarsBothComplementary (0 ms) [ RUN ] FindComplementaryPatternVarTest.LeftSubsetOfRight [ OK ] FindComplementaryPatternVarTest.LeftSubsetOfRight (0 ms) [ RUN ] FindComplementaryPatternVarTest.ThreeVarsAllSame [ OK ] FindComplementaryPatternVarTest.ThreeVarsAllSame (0 ms) [ RUN ] FindComplementaryPatternVarTest.PracticalPatternSimplification [ OK ] FindComplementaryPatternVarTest.PracticalPatternSimplification (0 ms) [ RUN ] FindComplementaryPatternVarTest.MuxTreeClockEnableDetection [ OK ] FindComplementaryPatternVarTest.MuxTreeClockEnableDetection (0 ms) [ RUN ] FindComplementaryPatternVarTest.AsymmetricPatterns [ OK ] FindComplementaryPatternVarTest.AsymmetricPatterns (0 ms) [ RUN ] FindComplementaryPatternVarTest.WireOffsetDistinction [ OK ] FindComplementaryPatternVarTest.WireOffsetDistinction (0 ms) [----------] 12 tests from FindComplementaryPatternVarTest (0 ms total) [----------] Global test environment tear-down [==========] 12 tests from 1 test suite ran. (0 ms total) [ PASSED ] 12 tests. make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src' PASS doubleslash.ys PASS uut_00042.ys PASS module_scope_case.v PASS bug2332.ys PASS uut_00003 PASS uut_00004 PASS fcall_smoke.ys PASS check.ys PASS check_2.ys PASS check_3.ys PASS opt_share_mux_tree.ys PASS opt_hier.tcl make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt' ...passed tests in ./opt PASS for_decl_no_init.ys PASS mem_arst.v PASS func_arg_mismatch_1.ys PASS check_4.ys PASS for_decl_no_sv.ys PASS uut_00005 PASS for_decl_shadow.ys PASS func_arg_mismatch_2.ys PASS func_arg_mismatch_3.ys PASS xprop_gt_5u3_2 PASS func_arg_mismatch_4.ys PASS sp_arst_e_x_re PASS module_scope_func.v PASS uut_00006 PASS chformal_check.ys PASS func_task_arg_copying.ys PASS mem2reg.v PASS func_tern_hint.ys PASS local_loop_var.sv PASS uut_00007 PASS func_typename_ret.ys PASS chformal_coverenable.ys PASS sp_arst_e_0_re PASS bug2759.ys PASS uut_00009 PASS uut_00008 PASS sp_arst_e_0 PASS mul.ys PASS xprop_gt_5s3_2 PASS uut_00011 PASS gen_block_end_label_only.ys PASS uut_00010 PASS const_arg_loop.ys PASS uut_00012 PASS sp_arst_e_any PASS uut_00037.ys PASS uut_00013 PASS gen_block_end_label_wrong.ys PASS sp_arst_e_any_re PASS uut_00014 PASS localparam_attr.v PASS uut_00015 PASS abc9.ys PASS sp_arst_e_init PASS loop_prefix_case.v PASS const_func.ys PASS uut_00016 PASS uut_00017 PASS genblk_case.ys PASS genblk_port_decl.ys PASS genblk_wire.ys PASS uut_00018 PASS muxtree.v PASS sp_arst_e_init_re PASS xprop_reduce_and_3u_3 PASS uut_00019 PASS named_genblk.v PASS rom.ys PASS celledges_shift.ys PASS uut_00020 PASS xprop_reduce_and_3s_3 PASS uut_00046.ys PASS const_func_block_var.ys PASS const_shift_empty_arg.ys PASS constant_drive_conflict.ys PASS multiplier.v PASS constcomment.ys PASS uut_00021 PASS sp_arst_n_x PASS sp_arst_n_x_re PASS constmsk_test.ys PASS uut_00047.ys PASS uut_00022 PASS countbits.ys PASS uut_00044.ys PASS cutpoint_blackbox.ys PASS cutpoint_whole.ys PASS uut_00023 PASS debugon.ys PASS deminout_unused.ys PASS loop_var_shadow.v PASS design.ys PASS nested_genblk_resolve.v PASS design1.ys PASS sp_arst_n_0 PASS design2.ys PASS uut_00024 PASS uut_00039.ys PASS fsm.ys PASS design_equal_fail.ys PASS design_equal_pass.ys PASS simple_ram.ys PASS uut_00025 PASS xprop_reduce_or_3u_3 PASS elab_sys_tasks.ys PASS uut_00026 PASS uut_00027 PASS equiv_make_make_assert.ys PASS equiv_assume.ys PASS uut_00045.ys PASS genfor_decl_no_init.ys PASS sp_arst_n_0_re PASS uut_00028 PASS param_attr.v PASS omsp_dbg_uart.v PASS uut_00029 PASS cxxrtl_value_fuzz make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/cxxrtl' ...passed tests in ./cxxrtl PASS shifter.ys PASS uut_00030 PASS sp_arst_n_any PASS dsp_simd.ys PASS xprop_reduce_or_3s_3 PASS uut_00031 PASS xprop_reduce_xor_3u_3 PASS sp_arst_n_any_re PASS mux.ys PASS uut_00032 PASS uut_00033 PASS generate.v PASS uut_00034 PASS equiv_opt_multiclock.ys PASS opt_lut_ins.ys PASS uut_00035 PASS sp_arst_n_init_re PASS sp_arst_n_init PASS tribuf.ys PASS blockram.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/analogdevices' ...passed tests in ./arch/analogdevices PASS macc.ys PASS xprop_reduce_xor_3s_3 PASS uut_00036 PASS uut_00048.ys PASS sp_srst_x_x PASS uut_00037 PASS equiv_opt_undef.ys PASS bug2972.ys PASS genfor_decl_no_sv.ys PASS xprop_reduce_bool_1u_1 PASS xprop_reduce_xnor_3u_3 PASS sp_srst_x_x_re PASS exec.ys PASS uut_00038 PASS xprop_reduce_xnor_3s_3 PASS sp_srst_0_x PASS sp_srst_0_x_re PASS genvar_loop_decl_1.ys PASS uut_00039 PASS genvar_loop_decl_2.ys PASS uut_00040 PASS genvar_loop_decl_3.ys PASS realexpr.v PASS paramods.v PASS global_parameter.ys PASS bug5574.ys PASS uut_00041 PASS fib.ys PASS cellmatch.ys PASS loops.v PASS uut_00043 PASS uut_00042 PASS sp_srst_0_0 PASS fib_tern.ys PASS xprop_reduce_bool_3u_3 PASS hidden_decl.ys PASS uut_00044 PASS repwhile.v PASS booth.ys PASS sp_srst_0_0_re PASS uut_00045 PASS cellname.ys PASS xilinx_dsp.ys PASS retime.v PASS fsm-arst.ys PASS clkbufmap.ys PASS uut_00046 PASS xprop_reduce_bool_3s_3 PASS formalff_declockgate.ys PASS uut_00049.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' ...passed tests in ./fsm PASS spram.ys PASS uut_00047 PASS ifdef_nest.ys PASS macro_arg_surrounding_spaces.v PASS uut_00048 PASS ifdef_unterminated.ys PASS uut_00049 PASS uut_00050 PASS process.v PASS constmap.ys PASS fsm.ys PASS func_port_implied_dir.ys PASS sp_srst_0_any PASS gen_if_null.ys PASS uut_00051 PASS global_scope.ys PASS xilinx_srl.ys PASS matching_end_labels.sv PASS uut_00052 PASS sp_srst_0_init PASS xprop_logic_not_1u_1 PASS gzip_verilog.ys PASS uut_00053 PASS sp_srst_0_any_re PASS help.ys PASS macros.v PASS hierarchy_defer.ys PASS incdec.ys PASS dff2ff.ys PASS dffinit.ys PASS hierarchy_generate.ys PASS xprop_reduce_bool_3s_1 PASS uut_00054 PASS sp_srst_0_init_re PASS include_self.ys PASS sp_srst_v_x PASS uut_00055 PASS localparam_no_default_1.ys PASS xprop_logic_not_3u_3 PASS uut_00056 PASS int_types.ys PASS uut_00057 PASS scopes.v PASS xprop_logic_not_3s_3 PASS sp_srst_v_x_re PASS sp_srst_v_0 PASS uut_00058 PASS macro_arg_spaces.sv PASS uut_00059 PASS uut_00060 PASS integer_real_bad_syntax.ys PASS hierarchy_param.ys PASS sp_srst_v_0_re PASS integer_range_bad_syntax.ys PASS uut_00061 PASS sign_part_assign.v PASS uut_00062 PASS json_escape_chars.ys PASS logic.ys PASS dfflegalize_adff.ys PASS signed_full_slice.v PASS xprop_logic_not_3s_1 PASS localparam_no_default_2.ys PASS uut_00063 PASS json_param_defaults.ys PASS signedexpr.v PASS cmp2lcu.ys PASS uut_00064 PASS sp_srst_v_any_ce PASS sp_srst_v_any_re_gated PASS sp_srst_v_any_re PASS sp_srst_v_any PASS sp_srst_v_any_ce_gated PASS macro_arg_tromp.ys PASS uut_00065 PASS mem2reg.v PASS json_scopeinfo.ys PASS dfflegalize_adlatch.ys PASS keep_hierarchy.ys PASS string_format.v PASS specify.v PASS uut_00066 PASS lcov.ys PASS uut_00067 PASS macro_unapplied.ys PASS sp_srst_v_init PASS uut_00068 PASS uut_00069 PASS uut_00070 PASS sp_srst_v_init_re PASS mem2reg_bounds_tern.v PASS uut_00071 PASS uut_00072 PASS mem_arst.v PASS uut_00073 PASS logger_error.ys PASS dfflegalize_adff_init.ys PASS xprop_logic_and_1u1_1 PASS uut_00074 PASS dfflegalize_adlatch_init.ys PASS dfflegalize_aldff.ys PASS uut_00075 PASS sp_srst_e_x PASS sp_srst_e_x_re PASS uut_00076 PASS undef_eqx_nex.v PASS memory.v PASS dfflegalize_aldff_init.ys PASS xprop_logic_and_3u3_3 PASS uut_00077 PASS subbytes.v PASS uut_00078 PASS memwr_port_connection.sv PASS sp_srst_e_0 PASS rotate.v PASS xprop_logic_or_1u1_1 PASS uut_00080 PASS xprop_logic_and_3s3_3 PASS uut_00081 PASS sincos.v PASS operators.v PASS uut_00079 PASS logger_nowarning.ys PASS macro_unapplied_newline.ys PASS dfflegalize_dff.ys PASS unnamed_block_decl.sv PASS xprop_logic_and_3s3_1 PASS uut_00084 PASS uut_00083 PASS uut_00082 PASS dfflegalize_dlatch.ys PASS ice40_mince_abc9.ys PASS dfflegalize_dffsr.ys PASS sp_srst_e_0_re PASS module_end_label.ys PASS sp_srst_e_any PASS uut_00085 PASS net_types.ys PASS package_end_label.ys PASS mem_bounds.ys PASS dfflegalize_dlatch_const.ys PASS module_scope.v PASS uut_00086 PASS module_scope_case.v PASS dfflegalize_dlatch_init.ys PASS uut_00087 PASS sp_srst_e_any_re PASS uut_00088 PASS logger_warn.ys PASS uut_00089 PASS sp_srst_e_init PASS logic.ys PASS task_func.v PASS uut_00090 PASS package_import_separate.ys PASS xprop_logic_or_3u3_3 PASS verilog_primitives.v PASS sp_srst_e_init_re PASS usb_phy_tests.v PASS logger_warning.ys PASS xilinx_dffopt.ys PASS uut_00091 PASS xprop_logic_or_3s3_1 PASS xprop_logic_or_3s3_3 PASS uut_00092 PASS module_scope_func.v PASS uut_00093 PASS logic_param_simple.ys PASS sp_srst_n_any PASS uut_00094 PASS package_import_specific.ys PASS sp_srst_n_x PASS sp_srst_n_0_re PASS uut_00095 PASS xprop_shl_4u3u_3 PASS uut_00096 PASS package_task_func.ys PASS values.v PASS mux.ys PASS sp_srst_n_x_re PASS param_default.ys PASS mem2reg.ys PASS dfflegalize_dlatchsr.ys PASS sp_srst_n_0 PASS sp_srst_n_init PASS uut_00097 PASS memory_word_as_index.ys PASS dfflegalize_mince.ys PASS uut_00098 PASS sp_srst_n_any_re PASS param_int_types.ys PASS sp_srst_n_init_re PASS uut_00099 make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/realmath' ...passed tests in ./realmath PASS nested_genblk_resolve.v PASS dfflegalize_minsrst.ys PASS named_genblk.v PASS xprop_shl_4s3u_3 PASS param_no_default_not_svmode.ys PASS dfflegalize_dlatchsr_init.ys PASS param_no_default.ys PASS wandwor.v PASS muxpack_wide_y.ys PASS param_struct.ys PASS param_no_default_unbound_2.ys PASS param_no_default_unbound_1.ys PASS xprop_shr_4s3u_3 PASS sp_srst_gv_x PASS param_no_default_unbound_4.ys PASS sp_srst_gv_x_re PASS dfflegalize_dffsr_init.ys PASS param_no_default_unbound_3.ys PASS xprop_shr_4u3u_3 PASS dfflegalize_sr.ys PASS param_no_default_unbound_5.ys PASS muxpack.ys PASS dfflibmap.ys PASS dfflegalize_inv.ys PASS omsp_dbg_uart.v PASS muxtree.v PASS ram_TDP.ys PASS dfflegalize_sr_init.ys PASS peepopt_formal.ys PASS dffunmap.ys PASS extractinv.ys PASS parameters_across_files.ys PASS sp_srst_gv_0 PASS tribuf.ys PASS peepopt.ys PASS dfflibmap_proc_formal.ys PASS muxcover.ys PASS param_attr.v PASS lut2bmux.ys PASS xprop_sshl_4s3u_3 PASS multiplier.v PASS xprop_sshl_4u3u_3 PASS lut2mux.ys PASS vloghammer.v PASS iopadmap.ys PASS pmux2shiftx.ys PASS xprop_sshr_4u3u_3 PASS module_not_derived.ys PASS past_signedness.ys PASS pmux2mux.ys PASS ram_SDP.ys PASS sp_srst_gv_0_re PASS prefix.ys PASS port_int_types.ys PASS wreduce.v PASS reset_auto_counter.ys PASS sp_srst_gv_any_re PASS priority_if_enc.ys PASS shifter.ys PASS techmap_chtype.ys PASS techmap_replace.ys PASS sp_srst_gv_any PASS paramods.v PASS wireinit.ys PASS sp_srst_gv_any_re_gated PASS roundtrip_proc.ys PASS xaiger2-5169.ys PASS memory.v PASS primitives.ys PASS printattr.ys PASS sp_srst_gv_any_ce PASS port_sign_extend.ys PASS process.v PASS dfflegalize_dff_init.ys PASS meminit.ys PASS sbvector.ys PASS rand_const.ys PASS sign_array_query.ys PASS shiftx2mux.ys PASS realexpr.v PASS specify-ifnone.ys PASS string-literals.ys PASS repwhile.v PASS sp_srst_gv_any_ce_gated PASS zinit.ys PASS size_cast.ys PASS xprop_sshr_4s3u_3 PASS clockgate.tcl PASS reg_wire_error.ys PASS sp_srst_gv_init_re PASS sp_srst_gv_init PASS struct_access.ys PASS rename_scramble_name.ys PASS sva-in-case-expr.ys PASS xprop_shift_4s3u_3 PASS wren_a4d4_NO_BYTE PASS task_attr.ys PASS rename_unescape.ys PASS widemux.ys PASS wren_a5d4_NO_BYTE PASS xprop_shift_4u3u_3 PASS retime.v PASS wren_a6d4_NO_BYTE PASS han-carlson.tcl PASS kogge-stone.tcl PASS dfflibmap_formal.ys PASS typedef_across_files.ys PASS typedef_const_shadow.ys PASS bug5495.sh PASS recursive_runtest.sh PASS xprop_mux_1 PASS rename_wire_move_to_cell.ys PASS mux.ys PASS xprop_shift_4u3s_3 PASS xprop_shift_4s3s_3 PASS rtlil_z_bits.ys PASS rtlil_signed_attribute.ys PASS wren_a3d8_NO_BYTE PASS typedef_legacy_conflict.ys PASS sklansky.tcl PASS xprop_shift_4u2s_8 PASS scopeinfo.ys PASS xprop_shiftx_4u2s_8 PASS xprop_shift_4s2s_8 PASS unbased_unsized.ys PASS wren_a4d8_NO_BYTE PASS scratchpad.ys PASS wren_a4d4_W4_B4 PASS script.ys PASS wren_a4d8_W8_B4 PASS wren_a4d8_W4_B4_separate PASS unbased_unsized_shift.ys PASS wren_a4d8_W8_B4_separate PASS mem_simple_4x1_runtest.sh make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' ...passed tests in ./techmap PASS xprop_mux_3 PASS setundef.ys PASS xprop_shiftx_4u3s_3 PASS wren_a4d8_W8_B8 PASS setundef_selection.ys PASS signedexpr.v PASS sformatf.ys PASS shregmap.ys PASS string_format.v PASS unbased_unsized_tern.ys PASS scopes.v PASS sign_part_assign.v PASS signed.ys PASS signed_full_slice.v PASS signext.ys PASS undef_eqx_nex.v PASS xprop_bmux_2_2 PASS wren_a4d8_W8_B8_separate PASS sim_const.ys PASS specify.ys PASS splitnets.ys PASS subbytes.v PASS xprop_bmux_1_2 PASS xprop_bmux_3_1 PASS unique0_if_enc.ys PASS src.ys PASS wren_a4d2w8_W16_B4_separate PASS wren_a4d2w8_W16_B4 PASS unnamed_block_decl.sv PASS xprop_demux_1_2 PASS sta.ys PASS unique_if.ys PASS mult.ys PASS wren_a4d4w4_W16_B4 PASS xprop_pmux_1_4 PASS usb_phy_tests.v PASS unique_if_else.ys PASS xprop_pmux_2_2 PASS xprop_pmux_3_1 PASS wren_a5d4w2_W16_B4 PASS stat.ys PASS verilog_primitives.v PASS unique_if_else_begin.ys PASS task_func.v PASS wren_a4d4w4_W16_B4_separate PASS xprop_demux_3_1 PASS stat_hierarchy.ys PASS stat_high_level.ys PASS unique_priority_case.ys PASS xprop_demux_2_2 PASS xprop_bweqx_1 PASS unique_if_enc.ys PASS stat_high_level2.ys PASS values.v PASS xprop_ff_1 PASS struct_access.ys PASS xprop_bwmux_1 PASS xprop_bweqx_3 PASS xprop_pmux_4_4 PASS submod_extract.ys PASS submod.ys PASS unique_priority_if.ys PASS unmatched_elsif.ys PASS wren_a5d4w2_W16_B4_separate PASS unmatched_else.ys PASS adffs.ys PASS sv_defines.ys PASS wren_a4d8w2_W16_B4 PASS xprop_ff_3 PASS xprop_bwmux_3 PASS xprop_dff_1pd PASS sv_defines_dup.ys PASS wren_a5d4w4_W16_B4 PASS wren_a5d4w4_W16_B4_separate PASS unmatched_endif_2.ys PASS unnamed_block.ys PASS unmatched_endif.ys PASS sv_defines_mismatch.ys PASS wren_a4d8w2_W16_B4_separate PASS unnamed_genblk.ys PASS sv_defines_too_few.ys PASS unreachable_case_sign.ys PASS wren_a5d8w1_W16_B4 PASS upto.ys PASS tcl_apis.ys PASS wren_a5d8w2_W16_B4 PASS wire_and_var.ys PASS xprop_dff_1nd PASS wren_a5d8w1_W16_B4_separate PASS void_func.ys PASS wrapcell.ys PASS vloghammer.v PASS tribuf.ys PASS wreduce.ys PASS wren_a4d16w1_W16_B4 PASS wren_a5d8w2_W16_B4_separate PASS xprop_dff_3pd PASS wreduce2.ys PASS rotate.v PASS xaiger.ys PASS local_include.sh PASS wren_a4d16w1_W16_B4_separate PASS write_gzip.ys PASS chparam.sh PASS wren_a4d4w2_W8_B8 PASS logger_cmd_error.sh PASS wandwor.v PASS wren_a4d4w2_W8_B8_separate PASS wren_a4d4w1_W8_B8 PASS hierarchy.sh PASS timeest.ys PASS wren_a4d4w1_W8_B8_separate PASS clk2fflogic_effects.sh PASS xprop_dffe_1pnd PASS logger_fail.sh PASS wren_a4d8w2_W8_B8_separate PASS mul.ys PASS wren_a4d8w2_W8_B8 PASS wren_a3d8w2_W8_B8 PASS wren_a3d8w2_W8_B8_separate PASS svalways.sh PASS xprop_dff_3nd PASS sv_implicit_ports.sh PASS mul.ys PASS wren_a4d2w4_W8_B4 PASS wren_a4d4w2_W8_B4 PASS wren_a4d4w4_W4_B4 PASS wren_a4d4w2_W8_B4_separate PASS wren_a4d2w4_W8_B4_separate PASS wren_a4d4w4_W4_B4_separate PASS async.sh PASS xprop_dffe_1nnd PASS wren_a4d4w4_W8_B4 PASS wren_a4d4w4_W8_B4_separate PASS geom_a5d32_wren PASS wren_a4d4w5_W4_B4 PASS wren_a4d4w5_W4_B4_separate PASS geom_a4d64_wren PASS partsel.v make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple' ...passed tests in ./simple PASS geom_a6d16_wren PASS geom_a7d6_wren PASS xprop_dffe_3nnd PASS pmgen_xilinx_srl.ys PASS geom_a5d64_wren PASS xprop_dffe_3pnd PASS pmgen_reduce.ys PASS geom_a7d4_wren PASS xprop_dffe_1ppd PASS geom_a7d8_wren PASS geom_a6d64_wren PASS geom_a8d4_wren PASS geom_a6d30_wren PASS geom_a7d17_wren PASS xprop_dffe_1npd PASS geom_a9d8_wren PASS geom_a8d6_wren PASS geom_a9d5_wren PASS geom_a9d4_wren PASS geom_a3d18_9b1B PASS geom_a4d18_9b1B PASS geom_a9d6_wren PASS geom_a4d4_9b1B PASS geom_a5d32_9b1B PASS geom_a6d4_9b1B PASS geom_a7d11_9b1B PASS wide_sdp_a8r1w1b1x1 PASS xprop_dffe_3ppd PASS geom_a11d1_9b1B PASS geom_a7d18_9b1B PASS sincos.v PASS wide_sdp_a7r1w1b1x1 PASS dsp_abc9.ys PASS wide_sdp_a6r1w1b1x1 PASS wide_sdp_a6r1w0b0x0 PASS wide_sdp_a6r0w0b0x0 PASS wide_sdp_a6r4w0b0x0 PASS wide_sdp_a6r3w0b0x0 PASS xprop_dffe_3npd make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/xprop' ...passed tests in ./xprop PASS wide_sdp_a6r2w0b0x0 PASS wide_sdp_a6r5w0b0x0 PASS wide_sdp_a6r0w2b0x0 PASS wide_sdp_a6r0w1b1x0 PASS shifter.ys PASS wide_sdp_a6r0w1b0x0 PASS wide_sdp_a7r1w0b0x0 PASS wide_sdp_a7r0w0b0x0 PASS wide_sdp_a6r0w3b2x0 PASS wide_sdp_a6r0w2b2x0 PASS wide_sdp_a7r3w0b0x0 PASS wide_sdp_a6r0w4b2x0 PASS wide_sdp_a7r2w0b0x0 PASS wide_sdp_a7r4w0b0x0 PASS wide_sdp_a7r0w1b0x0 PASS wide_sdp_a6r0w5b2x0 PASS wide_sdp_a7r0w1b1x0 PASS wide_sdp_a7r5w0b0x0 PASS wide_sdp_a7r0w2b0x0 PASS wide_sdp_a7r0w2b2x0 PASS wide_sp_mix_a8r1w1b1 PASS wide_sp_mix_a6r1w1b1 PASS wide_sdp_a7r0w3b2x0 PASS wide_sp_mix_a6r1w0b0 PASS wide_sp_mix_a7r1w1b1 PASS wide_sp_mix_a6r2w0b0 PASS nosrl.ys PASS wide_sp_mix_a6r3w0b0 PASS wide_sp_mix_a6r4w0b0 PASS wide_sp_mix_a6r0w1b0 PASS wide_sp_mix_a6r0w0b0 PASS wide_sp_mix_a6r0w1b1 PASS wide_sp_mix_a6r5w0b0 PASS wide_sdp_a7r0w4b2x0 PASS wide_sp_mix_a6r0w2b2 PASS wide_sp_mix_a6r0w2b0 PASS wide_sdp_a7r0w5b2x0 PASS wide_sp_mix_a7r1w0b0 PASS wide_sp_mix_a7r0w0b0 PASS wide_sp_mix_a6r0w3b2 PASS wide_sp_mix_a6r0w4b2 PASS wide_sp_mix_a7r3w0b0 PASS wide_sp_mix_a7r2w0b0 PASS wide_sp_mix_a7r0w1b1 PASS wide_sp_mix_a7r0w2b2 PASS wide_sp_mix_a7r0w1b0 PASS wide_sp_mix_a6r0w5b2 PASS wide_sp_mix_a7r4w0b0 PASS wide_sp_tied_a6r1w1b1 PASS wide_sp_mix_a7r5w0b0 PASS wide_sp_mix_a7r0w3b2 PASS wide_sp_mix_a7r0w2b0 PASS wide_sp_tied_a7r1w1b1 PASS wide_sp_tied_a6r1w0b0 PASS wide_sp_tied_a8r1w1b1 PASS wide_sp_tied_a6r0w0b0 PASS wide_sp_tied_a6r4w0b0 PASS wide_sp_mix_a7r0w4b2 PASS wide_sp_tied_a6r0w1b0 PASS wide_sp_tied_a6r0w1b1 PASS wide_sp_tied_a6r2w0b0 PASS wide_sp_tied_a6r0w2b0 PASS wide_sp_tied_a6r3w0b0 PASS wide_sp_tied_a6r5w0b0 PASS wide_sp_tied_a7r2w0b0 PASS wide_sp_mix_a7r0w5b2 PASS wide_sp_tied_a7r0w0b0 PASS wide_sp_tied_a6r0w2b2 PASS wide_sp_tied_a7r1w0b0 PASS wide_sp_tied_a6r0w3b2 PASS wide_sp_tied_a6r0w4b2 PASS wide_sp_tied_a7r3w0b0 PASS wide_sp_tied_a7r4w0b0 PASS wreduce.v PASS wide_sp_tied_a7r0w1b0 PASS wide_sp_tied_a7r0w2b0 PASS wide_sp_tied_a7r0w1b1 PASS wide_sp_tied_a6r0w5b2 PASS wide_sp_tied_a7r5w0b0 PASS wide_sp_tied_a7r0w3b2 PASS wide_write_a6r1w1b1 PASS wide_read_a8r1w1b1 PASS wide_sp_tied_a7r0w2b2 PASS wide_write_a7r1w1b1 PASS wide_read_a7r1w1b1 PASS wide_read_a6r1w1b1 PASS wide_write_a6r0w0b0 PASS wide_read_a6r0w0b0 PASS wide_sp_tied_a7r0w4b2 PASS wide_write_a8r1w1b1 PASS wide_read_a6r1w0b0 PASS wide_write_a6r1w0b0 PASS wide_read_a6r3w0b0 PASS wide_write_a6r2w0b0 PASS wide_write_a6r3w0b0 PASS wide_read_a6r2w0b0 PASS wide_read_a6r4w0b0 PASS wide_write_a6r0w1b0 PASS wide_read_a6r0w1b1 PASS wide_sp_tied_a7r0w5b2 PASS wide_read_a6r0w2b0 PASS wide_write_a6r0w1b1 PASS wide_write_a6r4w0b0 PASS wide_read_a6r0w1b0 PASS wide_write_a6r0w2b0 PASS wide_read_a6r5w0b0 PASS wide_write_a6r5w0b0 PASS wide_read_a6r0w2b2 PASS wide_write_a6r0w2b2 PASS wide_read_a6r0w3b2 PASS wide_read_a7r0w0b0 PASS wide_read_a7r1w0b0 PASS wide_write_a7r0w0b0 PASS wide_write_a7r1w0b0 PASS wide_write_a6r0w3b2 PASS wide_read_a6r0w4b2 PASS wide_write_a7r2w0b0 PASS wide_read_a7r2w0b0 PASS wide_write_a7r3w0b0 PASS wide_write_a6r0w4b2 PASS wide_read_a7r3w0b0 PASS wide_read_a7r0w1b0 PASS wide_read_a7r4w0b0 PASS wide_read_a7r5w0b0 PASS wide_write_a7r0w1b0 PASS wide_write_a7r4w0b0 PASS wide_read_a7r0w2b0 PASS wide_read_a7r0w1b1 PASS wide_write_a7r0w2b0 PASS wide_write_a6r0w5b2 PASS wide_write_a7r0w2b2 PASS wide_read_a6r0w5b2 PASS wide_write_a7r0w1b1 PASS wide_read_a7r0w2b2 PASS wide_read_a7r0w3b2 PASS wide_write_a7r5w0b0 PASS wide_write_a7r0w3b2 PASS wide_write_a7r0w4b2 PASS wide_read_a7r0w4b2 PASS quad_port_a2d2 PASS wide_quad_a4w2r1 PASS wide_oct_a4w2r1 PASS quad_port_a5d2 PASS wide_oct_a4w2r2 PASS quad_port_a4d8 PASS quad_port_a6d2 PASS quad_port_a4d2 PASS wide_quad_a4w2r2 PASS plugin.sh PASS quad_port_a4d4 PASS wide_write_a7r0w5b2 PASS wide_oct_a4w2r3 PASS wide_quad_a4w2r3 PASS wide_quad_a4w2r4 PASS wide_read_a7r0w5b2 PASS wide_quad_a4w2r5 PASS wide_oct_a4w2r4 PASS wide_oct_a4w2r5 PASS wide_quad_a4w2r6 PASS wide_oct_a4w2r6 PASS wide_oct_a4w4r1 PASS wide_oct_a4w2r7 PASS wide_quad_a4w4r1 PASS wide_quad_a4w2r8 PASS wide_quad_a4w4r4 PASS wide_oct_a4w2r9 PASS wide_oct_a4w2r8 PASS wide_quad_a4w2r7 PASS wide_oct_a4w4r4 PASS wide_quad_a4w2r9 PASS wide_quad_a4w4r6 PASS wide_quad_a5w2r1 PASS wide_oct_a5w2r1 PASS wide_oct_a4w4r6 PASS wide_quad_a4w4r9 PASS wide_quad_a5w2r4 PASS wide_oct_a5w2r4 PASS wide_oct_a4w4r9 PASS gclken PASS wide_quad_a5w2r9 PASS no_reset PASS grden PASS wide_oct_a5w2r9 PASS gclken_ce PASS ezcmdline_plugin.sh PASS ungated PASS exclwr PASS rom_case PASS grden_ce PASS rom_case_block PASS excl_rst PASS wr_rst_byte PASS transwr PASS trans_byte PASS trans_rst PASS wr_byte PASS rst_wr_byte PASS rdenrst_wr_byte make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' ...passed tests in ./memlib PASS operators.v PASS macc.sh PASS dffs.ys PASS macc.ys PASS mux_lut4.ys PASS mul_unsigned.ys PASS adffs.ys PASS latches.ys PASS tribuf.sh PASS func_upto.ys PASS fuse_mac.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' ...passed tests in ./arch/nexus PASS dffs.ys PASS bug1644.ys PASS dff.ys PASS dsp_cascade.ys PASS attributes_test.ys PASS luttrees.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' ...passed tests in ./arch/gatemate PASS ioff.ys PASS mux.ys PASS lutram.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' ...passed tests in ./arch/gowin PASS dynamic_part_select.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/various' ...passed tests in ./various PASS latches.ys PASS add_sub.ys PASS dsp.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/microchip' ...passed tests in ./arch/microchip PASS adffs.ys PASS asym_ram_sdp.ys PASS memories.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' ...passed tests in ./arch/ecp5 PASS abc9_dff.ys PASS dynamic_range_lhs.sh make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' ...passed tests in ./verilog PASS meminit.ys PASS mux.ys PASS priority_memory.ys PASS t_mem2.ys PASS t_mem3.ys PASS lutram.ys PASS t_mem6.ys PASS t_mem4.ys PASS partsel.v make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' ...passed tests in ./simple_abc9 PASS t_mem5.ys PASS t_mem1.ys PASS t_mem0.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' ...passed tests in ./arch/quicklogic/qlf_k6n10f PASS dsp_preadder_sub.ys PASS blockram.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' ...passed tests in ./arch/xilinx PASS memories.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' ...passed tests in ./arch/ice40 PASS lutram.ys make[2]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' ...passed tests in ./arch/nanoxplore Passed "make vanilla-test". ========================== Tests: 2179 Passed: 2179 Failed: 0 ========================== make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests' >>> yosys: Entering fakeroot... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys; fi if [ -n "strip" ]; then strip /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys-filterlib; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys cp -r share/. /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys/. mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/ if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/libyosys.so; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.14/site-packages/pyosys cp .//pyosys/__init__.py /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.14/site-packages/pyosys/__init__.py cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.14/site-packages/pyosys/libyosys.so cp -r share /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.14/site-packages/pyosys '/home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.14/site-packages/pyosys/libyosys.so' -> '/usr/lib/yosys/libyosys.so' >>> yosys-dev*: Running split function dev... 'usr/bin/yosys-config' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/usr/bin/yosys-config' './usr/share/yosys/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/share/yosys/include' './usr/lib/python3.14/site-packages/pyosys/share/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/lib/python3.14/site-packages/pyosys/share/include' >>> yosys-dev*: Preparing subpackage yosys-dev... >>> yosys-dev*: Stripping binaries >>> yosys-dev*: Running postcheck for yosys-dev >>> py3-yosys*: Running split function py3... 'usr/lib/python3.14' -> '/home/buildozer/aports/testing/yosys/pkg/py3-yosys/usr/lib/python3.14' >>> py3-yosys*: Preparing subpackage py3-yosys... >>> py3-yosys*: Running postcheck for py3-yosys >>> yosys*: Running postcheck for yosys >>> yosys*: Preparing package yosys... >>> yosys*: Stripping binaries >>> yosys*: Scanning shared objects >>> yosys-dev*: Scanning shared objects >>> yosys*: Tracing dependencies... abc so:libc.musl-aarch64.so.1 so:libffi.so.8 so:libgcc_s.so.1 so:libpython3.14.so.1.0 so:libreadline.so.8 so:libstdc++.so.6 so:libtcl8.6.so so:libz.so.1 >>> yosys*: Package size: 64.5 MB >>> yosys*: Compressing data... >>> yosys*: Create checksum... >>> yosys*: Create yosys-0.66-r0.apk >>> yosys-dev*: Tracing dependencies... python3~3.14 >>> yosys-dev*: Package size: 1.3 MB >>> yosys-dev*: Compressing data... >>> yosys-dev*: Create checksum... >>> yosys-dev*: Create yosys-dev-0.66-r0.apk >>> py3-yosys*: Tracing dependencies... python3 yosys=0.66-r0 python3~3.14 yosys=0.66-r0 >>> py3-yosys*: Package size: 9.2 MB >>> py3-yosys*: Compressing data... >>> py3-yosys*: Create checksum... >>> py3-yosys*: Create py3-yosys-0.66-r0.apk >>> yosys: Build complete at Wed, 15 Jul 2026 03:31:30 +0000 elapsed time 0h 11m 20s >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Uninstalling dependencies... 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(2.88.2-r0) (295/365) Purging gnutls (3.8.13-r0) (296/365) Purging graphite2 (1.3.15-r0) (297/365) Purging icu (78.1-r0) (298/365) Purging icu-libs (78.1-r0) (299/365) Purging icu-data-en (78.1-r0) (300/365) Purging lcms2 (2.19-r0) (301/365) Purging util-linux-dev (2.42.2-r0) (302/365) Purging libfdisk (2.42.2-r0) (303/365) Purging liblastlog2 (2.42.2-r0) (304/365) Purging libmount (2.42.2-r0) (305/365) Purging libsmartcols (2.42.2-r0) (306/365) Purging libblkid (2.42.2-r0) (307/365) Purging libxrender-dev (0.9.12-r0) (308/365) Purging libxrender (0.9.12-r0) (309/365) Purging libxext-dev (1.3.7-r0) (310/365) Purging libx11-dev (1.8.13-r0) (311/365) Purging xtrans (1.6.0-r0) (312/365) Purging libxcb-dev (1.17.0-r2) (313/365) Purging xcb-proto (1.17.0-r1) (314/365) Purging python3 (3.14.5-r2) (315/365) Purging libxdmcp-dev (1.1.5-r1) (316/365) Purging libxi (1.8.3-r0) (317/365) Purging libxext (1.3.7-r0) (318/365) Purging libx11 (1.8.13-r0) (319/365) Purging libxcb (1.17.0-r2) (320/365) Purging libxdmcp (1.1.5-r1) (321/365) Purging libbsd (0.12.2-r0) (322/365) Purging libbz2 (1.0.8-r6) (323/365) Purging libeconf (0.8.3-r0) (324/365) Purging libffi-dev (3.5.2-r1) (325/365) Purging linux-headers (7.1.3-r0) (326/365) Purging wayland-libs-client (1.25.0-r0) (327/365) Purging p11-kit (0.26.2-r1) (328/365) Purging libffi (3.5.2-r1) (329/365) Purging libformw (6.6_p20260516-r0) (330/365) Purging libsm (1.2.6-r0) (331/365) Purging libice (1.1.2-r0) (332/365) Purging libjpeg-turbo-dev (3.1.3-r0) (333/365) Purging libturbojpeg (3.1.3-r0) (334/365) Purging libjpeg-turbo (3.1.3-r0) (335/365) Purging libmd (1.2.0-r0) (336/365) Purging libmenuw (6.6_p20260516-r0) (337/365) Purging libpanelw (6.6_p20260516-r0) (338/365) Purging libpng-dev (1.6.58-r1) (339/365) Purging libpng (1.6.58-r1) (340/365) Purging libseccomp (2.6.0-r2) (341/365) Purging libwebp-dev (1.6.0-r0) (342/365) Purging libwebpdecoder (1.6.0-r0) (343/365) Purging libwebpdemux (1.6.0-r0) (344/365) Purging libwebpmux (1.6.0-r0) (345/365) Purging libwebp (1.6.0-r0) (346/365) Purging libsharpyuv (1.6.0-r0) (347/365) Purging libtasn1 (4.21.0-r0) (348/365) Purging libuuid (2.42.2-r0) (349/365) Purging libxau-dev (1.0.12-r0) (350/365) Purging libxau (1.0.12-r0) (351/365) Purging libxml2 (2.13.9-r2) (352/365) Purging linux-pam (1.7.1-r2) (353/365) Purging mpdecimal (4.0.1-r0) (354/365) Purging nettle (3.10.2-r0) (355/365) Purging pixman-dev (0.46.4-r0) (356/365) Purging pixman (0.46.4-r0) (357/365) Purging sqlite-dev (3.53.3-r0) (358/365) Purging sqlite-libs (3.53.3-r0) (359/365) Purging sqlite (3.53.3-r0) (360/365) Purging readline (8.3.3-r1) (361/365) Purging utmps-libs (0.1.3.4-r0) (362/365) Purging skalibs-libs (2.15.1.0-r0) (363/365) Purging xorgproto (2025.1-r0) (364/365) Purging xz-libs (5.8.3-r0) (365/365) Purging zlib-dev (1.3.2-r0) Executing busybox-1.38.0-r1.trigger OK: 433.3 MiB in 109 packages >>> yosys: Updating the testing/aarch64 repository index... >>> yosys: Signing the index...