>>> yosys: Building testing/yosys 0.42-r0 (using abuild 3.13.0-r3) started Wed, 19 Jun 2024 15:15:26 +0000 >>> yosys: Checking sanity of /home/buildozer/aports/testing/yosys/APKBUILD... >>> yosys: Analyzing dependencies... >>> yosys: Installing for build: build-base abc bash bison boost-dev flex gawk graphviz-dev libffi-dev lld protobuf-dev python3 readline-dev tcl-dev zlib-dev iverilog (1/337) Installing readline (8.2.10-r0) (2/337) Installing abc (0_git20240102-r0) (3/337) Installing bash (5.2.26-r0) Executing bash-5.2.26-r0.post-install (4/337) Installing m4 (1.4.19-r3) (5/337) Installing bison (3.8.2-r1) (6/337) Installing boost1.84-atomic (1.84.0-r1) (7/337) Installing boost1.84-chrono (1.84.0-r1) (8/337) Installing boost1.84-container (1.84.0-r1) (9/337) Installing boost1.84-context (1.84.0-r1) (10/337) Installing boost1.84-contract (1.84.0-r1) (11/337) Installing boost1.84-coroutine (1.84.0-r1) (12/337) Installing boost1.84-date_time (1.84.0-r1) (13/337) Installing boost1.84-fiber (1.84.0-r1) (14/337) Installing boost1.84-filesystem (1.84.0-r1) (15/337) Installing boost1.84-graph (1.84.0-r1) (16/337) Installing libbz2 (1.0.8-r6) (17/337) Installing xz-libs (5.6.2-r0) (18/337) Installing boost1.84-iostreams (1.84.0-r1) (19/337) Installing boost1.84-thread (1.84.0-r1) (20/337) Installing icu-data-en (74.2-r0) Executing icu-data-en-74.2-r0.post-install * * If you need ICU with non-English locales and legacy charset support, install * package icu-data-full. * (21/337) Installing icu-libs (74.2-r0) (22/337) Installing boost1.84-locale (1.84.0-r1) (23/337) Installing boost1.84-log (1.84.0-r1) (24/337) Installing boost1.84-log_setup (1.84.0-r1) (25/337) Installing boost1.84-math (1.84.0-r1) (26/337) Installing boost1.84-prg_exec_monitor (1.84.0-r1) (27/337) Installing boost1.84-program_options (1.84.0-r1) (28/337) Installing libffi (3.4.6-r0) (29/337) Installing gdbm (1.23-r1) (30/337) Installing mpdecimal (4.0.0-r0) (31/337) Installing libpanelw (6.4_p20240420-r0) (32/337) Installing sqlite-libs (3.46.0-r0) (33/337) Installing python3 (3.12.3-r1) (34/337) Installing python3-pycache-pyc0 (3.12.3-r1) (35/337) Installing pyc (3.12.3-r1) (36/337) Installing python3-pyc (3.12.3-r1) (37/337) Installing boost1.84-python3 (1.84.0-r1) (38/337) Installing boost1.84-random (1.84.0-r1) (39/337) Installing boost1.84-regex (1.84.0-r1) (40/337) Installing boost1.84-serialization (1.84.0-r1) (41/337) Installing boost1.84-stacktrace_basic (1.84.0-r1) (42/337) Installing boost1.84-stacktrace_noop (1.84.0-r1) (43/337) Installing boost1.84-system (1.84.0-r1) (44/337) Installing boost1.84-timer (1.84.0-r1) (45/337) Installing boost1.84-type_erasure (1.84.0-r1) (46/337) Installing boost1.84-unit_test_framework (1.84.0-r1) (47/337) Installing boost1.84-url (1.84.0-r1) (48/337) Installing boost1.84-wave (1.84.0-r1) (49/337) Installing boost1.84-wserialization (1.84.0-r1) (50/337) Installing boost1.84-json (1.84.0-r1) (51/337) Installing boost1.84-nowide (1.84.0-r1) (52/337) Installing boost1.84-libs (1.84.0-r1) (53/337) Installing boost1.84 (1.84.0-r1) (54/337) Installing linux-headers (6.6-r0) (55/337) Installing bzip2-dev (1.0.8-r6) (56/337) Installing icu (74.2-r0) (57/337) Installing icu-dev (74.2-r0) (58/337) Installing xz (5.6.2-r0) (59/337) Installing xz-dev (5.6.2-r0) (60/337) Installing zlib-dev (1.3.1-r1) (61/337) Installing zstd (1.5.6-r0) (62/337) Installing zstd-dev (1.5.6-r0) (63/337) Installing boost1.84-dev (1.84.0-r1) (64/337) Installing boost-dev (1.84.0-r1) (65/337) Installing flex (2.6.4-r6) (66/337) Installing gawk (5.3.0-r1) (67/337) Installing cairo-tools (1.18.0-r0) (68/337) Installing libpng (1.6.43-r0) (69/337) Installing freetype (2.13.2-r0) (70/337) Installing fontconfig (2.15.0-r1) (71/337) Installing expat (2.6.2-r0) (72/337) Installing expat-dev (2.6.2-r0) (73/337) Installing brotli (1.1.0-r2) (74/337) Installing brotli-dev (1.1.0-r2) (75/337) Installing libpng-dev (1.6.43-r0) (76/337) Installing freetype-dev (2.13.2-r0) (77/337) Installing fontconfig-dev (2.15.0-r1) (78/337) Installing libxau (1.0.11-r4) (79/337) Installing xorgproto (2024.1-r0) (80/337) Installing libxau-dev (1.0.11-r4) (81/337) Installing libmd (1.1.0-r0) (82/337) Installing libbsd (0.12.2-r0) (83/337) Installing libxdmcp (1.1.5-r1) (84/337) Installing libxcb (1.16.1-r0) (85/337) Installing libx11 (1.8.9-r1) (86/337) Installing libxext (1.3.6-r2) (87/337) Installing xcb-proto (1.16.0-r1) (88/337) Installing xcb-proto-pyc (1.16.0-r1) (89/337) Installing libxdmcp-dev (1.1.5-r1) (90/337) Installing libxcb-dev (1.16.1-r0) (91/337) Installing xtrans (1.5.0-r0) (92/337) Installing libx11-dev (1.8.9-r1) (93/337) Installing libxext-dev (1.3.6-r2) (94/337) Installing libxrender (0.9.11-r5) (95/337) Installing libxrender-dev (0.9.11-r5) (96/337) Installing pixman (0.43.2-r0) (97/337) Installing pixman-dev (0.43.2-r0) (98/337) Installing util-macros (1.20.0-r0) (99/337) Installing xcb-util (0.4.1-r3) (100/337) Installing xcb-util-dev (0.4.1-r3) (101/337) Installing cairo (1.18.0-r0) (102/337) Installing libintl (0.22.5-r0) (103/337) Installing libeconf (0.6.3-r0) (104/337) Installing libblkid (2.40.1-r1) (105/337) Installing libmount (2.40.1-r1) (106/337) Installing glib (2.80.3-r0) (107/337) Installing cairo-gobject (1.18.0-r0) (108/337) Installing libxml2 (2.12.7-r0) (109/337) Installing libxml2-utils (2.12.7-r0) (110/337) Installing docbook-xml (4.5-r9) Executing docbook-xml-4.5-r9.post-install (111/337) Installing libgpg-error (1.49-r0) (112/337) Installing libgcrypt (1.10.3-r0) (113/337) Installing libxslt (1.1.39-r1) (114/337) Installing docbook-xsl (1.79.2-r9) Executing docbook-xsl-1.79.2-r9.post-install (115/337) Installing gettext-asprintf (0.22.5-r0) (116/337) Installing gettext-libs (0.22.5-r0) (117/337) Installing gettext-envsubst (0.22.5-r0) (118/337) Installing gettext (0.22.5-r0) (119/337) Installing gettext-dev (0.22.5-r0) (120/337) Installing py3-parsing (3.1.2-r1) (121/337) Installing py3-parsing-pyc (3.1.2-r1) (122/337) Installing py3-packaging (24.1-r0) (123/337) Installing py3-packaging-pyc (24.1-r0) (124/337) Installing libffi-dev (3.4.6-r0) (125/337) Installing bsd-compat-headers (0.7.2-r6) (126/337) Installing libformw (6.4_p20240420-r0) (127/337) Installing libmenuw (6.4_p20240420-r0) (128/337) Installing libncurses++ (6.4_p20240420-r0) (129/337) Installing ncurses-dev (6.4_p20240420-r0) (130/337) Installing libedit-dev (20240517.3.1-r0) (131/337) Installing libpcre2-16 (10.43-r0) (132/337) Installing libpcre2-32 (10.43-r0) (133/337) Installing pcre2-dev (10.43-r0) (134/337) Installing libuuid (2.40.1-r1) (135/337) Installing libfdisk (2.40.1-r1) (136/337) Installing libsmartcols (2.40.1-r1) (137/337) Installing sqlite (3.46.0-r0) (138/337) Installing sqlite-dev (3.46.0-r0) (139/337) Installing util-linux (2.40.1-r1) (140/337) Installing dmesg (2.40.1-r1) (141/337) Installing setarch (2.40.1-r1) (142/337) Installing util-linux-misc (2.40.1-r1) (143/337) Installing skalibs (2.14.2.0-r0) (144/337) Installing utmps-libs (0.1.2.2-r1) (145/337) Installing linux-pam (1.6.0-r0) (146/337) Installing runuser (2.40.1-r1) (147/337) Installing mount (2.40.1-r1) (148/337) Installing losetup (2.40.1-r1) (149/337) Installing hexdump (2.40.1-r1) (150/337) Installing uuidgen (2.40.1-r1) (151/337) Installing blkid (2.40.1-r1) (152/337) Installing sfdisk (2.40.1-r1) (153/337) Installing mcookie (2.40.1-r1) (154/337) Installing agetty (2.40.1-r1) (155/337) Installing wipefs (2.40.1-r1) (156/337) Installing cfdisk (2.40.1-r1) (157/337) Installing umount (2.40.1-r1) (158/337) Installing flock (2.40.1-r1) (159/337) Installing lsblk (2.40.1-r1) (160/337) Installing libcap-ng (0.8.5-r0) (161/337) Installing setpriv (2.40.1-r1) (162/337) Installing logger (2.40.1-r1) (163/337) Installing partx (2.40.1-r1) (164/337) Installing fstrim (2.40.1-r1) (165/337) Installing findmnt (2.40.1-r1) (166/337) Installing util-linux-dev (2.40.1-r1) (167/337) Installing glib-dev (2.80.3-r0) (168/337) Installing cairo-dev (1.18.0-r0) (169/337) Installing libice (1.1.1-r6) (170/337) Installing libsm (1.2.4-r4) (171/337) Installing libxt (1.3.0-r5) (172/337) Installing libxpm (3.5.17-r0) (173/337) Installing aom-libs (3.9.1-r0) (174/337) Installing libdav1d (1.4.3-r0) (175/337) Installing libsharpyuv (1.3.2-r0) (176/337) Installing libavif (1.0.4-r0) (177/337) Installing libjpeg-turbo (3.0.3-r0) (178/337) Installing libwebp (1.3.2-r0) (179/337) Installing tiff (4.6.0t-r0) (180/337) Installing libgd (2.3.3-r9) (181/337) Installing gd (2.3.3-r9) (182/337) Installing perl (5.40.0-r0) (183/337) Installing libavif-dev (1.0.4-r0) (184/337) Installing libturbojpeg (3.0.3-r0) (185/337) Installing libjpeg-turbo-dev (3.0.3-r0) (186/337) Installing libtiffxx (4.6.0t-r0) (187/337) Installing libwebpdecoder (1.3.2-r0) (188/337) Installing libwebpdemux (1.3.2-r0) (189/337) Installing libwebpmux (1.3.2-r0) (190/337) Installing libwebp-dev (1.3.2-r0) (191/337) Installing tiff-dev (4.6.0t-r0) (192/337) Installing libxpm-dev (3.5.17-r0) (193/337) Installing gd-dev (2.3.3-r9) (194/337) Installing libgmpxx (6.3.0-r1) (195/337) Installing gmp-dev (6.3.0-r1) (196/337) Installing libice-dev (1.1.1-r6) (197/337) Installing libsm-dev (1.2.4-r4) (198/337) Installing libxft (2.3.8-r3) (199/337) Installing graphite2 (1.3.14-r6) (200/337) Installing harfbuzz (8.5.0-r0) (201/337) Installing fribidi (1.0.15-r0) (202/337) Installing pango (1.52.2-r0) (203/337) Installing pango-tools (1.52.2-r0) (204/337) Installing fribidi-dev (1.0.15-r0) (205/337) Installing harfbuzz-cairo (8.5.0-r0) (206/337) Installing harfbuzz-gobject (8.5.0-r0) (207/337) Installing harfbuzz-icu (8.5.0-r0) (208/337) Installing harfbuzz-subset (8.5.0-r0) (209/337) Installing graphite2-dev (1.3.14-r6) (210/337) Installing harfbuzz-dev (8.5.0-r0) (211/337) Installing libxft-dev (2.3.8-r3) (212/337) Installing pango-dev (1.52.2-r0) (213/337) Installing python3-dev (3.12.3-r1) (214/337) Installing graphviz-libs (11.0.0-r0) (215/337) Installing graphviz-dev (11.0.0-r0) (216/337) Installing llvm18-libs (18.1.7-r0) (217/337) Installing lld-libs (18.1.7-r0) (218/337) Installing scudo-malloc (17.0.6-r0) (219/337) Installing lld (18.1.7-r0) (220/337) Installing abseil-cpp-raw-logging-internal (20230802.1-r0) (221/337) Installing abseil-cpp-log-internal-globals (20230802.1-r0) (222/337) Installing abseil-cpp-time-zone (20230802.1-r0) (223/337) Installing abseil-cpp-log-initialize (20230802.1-r0) (224/337) Installing abseil-cpp-city (20230802.1-r0) (225/337) Installing abseil-cpp-low-level-hash (20230802.1-r0) (226/337) Installing abseil-cpp-hash (20230802.1-r0) (227/337) Installing abseil-cpp-log-internal-nullguard (20230802.1-r0) (228/337) Installing abseil-cpp-int128 (20230802.1-r0) (229/337) Installing abseil-cpp-strings-internal (20230802.1-r0) (230/337) Installing abseil-cpp-strings (20230802.1-r0) (231/337) Installing abseil-cpp-log-internal-check-op (20230802.1-r0) (232/337) Installing abseil-cpp-spinlock-wait (20230802.1-r0) (233/337) Installing abseil-cpp-base (20230802.1-r0) (234/337) Installing abseil-cpp-log-internal-conditions (20230802.1-r0) (235/337) Installing abseil-cpp-stacktrace (20230802.1-r0) (236/337) Installing abseil-cpp-symbolize (20230802.1-r0) (237/337) Installing abseil-cpp-examine-stack (20230802.1-r0) (238/337) Installing abseil-cpp-log-globals (20230802.1-r0) (239/337) Installing abseil-cpp-str-format-internal (20230802.1-r0) (240/337) Installing abseil-cpp-time (20230802.1-r0) (241/337) Installing abseil-cpp-log-internal-format (20230802.1-r0) (242/337) Installing abseil-cpp-log-sink (20230802.1-r0) (243/337) Installing abseil-cpp-kernel-timeout-internal (20230802.1-r0) (244/337) Installing abseil-cpp-malloc-internal (20230802.1-r0) (245/337) Installing abseil-cpp-synchronization (20230802.1-r0) (246/337) Installing abseil-cpp-log-internal-log-sink-set (20230802.1-r0) (247/337) Installing abseil-cpp-log-internal-proto (20230802.1-r0) (248/337) Installing abseil-cpp-strerror (20230802.1-r0) (249/337) Installing abseil-cpp-log-internal-message (20230802.1-r0) (250/337) Installing abseil-cpp-raw-hash-set (20230802.1-r0) (251/337) Installing abseil-cpp-crc-internal (20230802.1-r0) (252/337) Installing abseil-cpp-crc32c (20230802.1-r0) (253/337) Installing abseil-cpp-crc-cord-state (20230802.1-r0) (254/337) Installing abseil-cpp-throw-delegate (20230802.1-r0) (255/337) Installing abseil-cpp-cord-internal (20230802.1-r0) (256/337) Installing abseil-cpp-exponential-biased (20230802.1-r0) (257/337) Installing abseil-cpp-cordz-functions (20230802.1-r0) (258/337) Installing abseil-cpp-cordz-handle (20230802.1-r0) (259/337) Installing abseil-cpp-cordz-info (20230802.1-r0) (260/337) Installing abseil-cpp-cord (20230802.1-r0) (261/337) Installing abseil-cpp-status (20230802.1-r0) (262/337) Installing abseil-cpp-statusor (20230802.1-r0) (263/337) Installing abseil-cpp-die-if-null (20230802.1-r0) (264/337) Installing libprotobuf (24.4-r1) (265/337) Installing libprotoc (24.4-r1) (266/337) Installing protoc (24.4-r1) (267/337) Installing libprotobuf-lite (24.4-r1) (268/337) Installing abseil-cpp-atomic-hook-test-helper (20230802.1-r0) (269/337) Installing abseil-cpp-bad-any-cast-impl (20230802.1-r0) (270/337) Installing abseil-cpp-bad-optional-access (20230802.1-r0) (271/337) Installing abseil-cpp-bad-variant-access (20230802.1-r0) (272/337) Installing abseil-cpp-civil-time (20230802.1-r0) (273/337) Installing abseil-cpp-cordz-sample-token (20230802.1-r0) (274/337) Installing abseil-cpp-crc-cpu-detect (20230802.1-r0) (275/337) Installing abseil-cpp-debugging-internal (20230802.1-r0) (276/337) Installing abseil-cpp-demangle-internal (20230802.1-r0) (277/337) Installing gtest (1.14.0-r2) (278/337) Installing abseil-cpp-exception-safety-testing (20230802.1-r0) (279/337) Installing abseil-cpp-failure-signal-handler (20230802.1-r0) (280/337) Installing abseil-cpp-flags-commandlineflag-internal (20230802.1-r0) (281/337) Installing abseil-cpp-flags-commandlineflag (20230802.1-r0) (282/337) Installing abseil-cpp-flags-program-name (20230802.1-r0) (283/337) Installing abseil-cpp-flags-config (20230802.1-r0) (284/337) Installing abseil-cpp-flags-internal (20230802.1-r0) (285/337) Installing abseil-cpp-flags-marshalling (20230802.1-r0) (286/337) Installing abseil-cpp-flags-private-handle-accessor (20230802.1-r0) (287/337) Installing abseil-cpp-flags-reflection (20230802.1-r0) (288/337) Installing abseil-cpp-flags-usage (20230802.1-r0) (289/337) Installing abseil-cpp-flags-usage-internal (20230802.1-r0) (290/337) Installing abseil-cpp-flags-parse (20230802.1-r0) (291/337) Installing abseil-cpp-flags (20230802.1-r0) (292/337) Installing abseil-cpp-graphcycles-internal (20230802.1-r0) (293/337) Installing abseil-cpp-hash-generator-testing (20230802.1-r0) (294/337) Installing abseil-cpp-hashtablez-sampler (20230802.1-r0) (295/337) Installing abseil-cpp-leak-check (20230802.1-r0) (296/337) Installing abseil-cpp-log-entry (20230802.1-r0) (297/337) Installing abseil-cpp-log-flags (20230802.1-r0) (298/337) Installing abseil-cpp-log-severity (20230802.1-r0) (299/337) Installing abseil-cpp-log-internal-test-actions (20230802.1-r0) (300/337) Installing abseil-cpp-log-internal-test-helpers (20230802.1-r0) (301/337) Installing abseil-cpp-log-internal-test-matchers (20230802.1-r0) (302/337) Installing abseil-cpp-per-thread-sem-test-common (20230802.1-r0) (303/337) Installing abseil-cpp-periodic-sampler (20230802.1-r0) (304/337) Installing abseil-cpp-pow10-helper (20230802.1-r0) (305/337) Installing abseil-cpp-random-distributions (20230802.1-r0) (306/337) Installing abseil-cpp-random-internal-distribution-test-util (20230802.1-r0) (307/337) Installing abseil-cpp-random-internal-platform (20230802.1-r0) (308/337) Installing abseil-cpp-random-internal-randen-slow (20230802.1-r0) (309/337) Installing abseil-cpp-random-internal-randen (20230802.1-r0) (310/337) Installing abseil-cpp-random-internal-seed-material (20230802.1-r0) (311/337) Installing abseil-cpp-random-seed-gen-exception (20230802.1-r0) (312/337) Installing abseil-cpp-random-internal-pool-urbg (20230802.1-r0) (313/337) Installing abseil-cpp-random-internal-randen-hwaes-impl (20230802.1-r0) (314/337) Installing abseil-cpp-random-internal-randen-hwaes (20230802.1-r0) (315/337) Installing abseil-cpp-random-seed-sequences (20230802.1-r0) (316/337) Installing gmock (1.14.0-r2) (317/337) Installing abseil-cpp-scoped-mock-log (20230802.1-r0) (318/337) Installing abseil-cpp-scoped-set-env (20230802.1-r0) (319/337) Installing abseil-cpp-spinlock-test-common (20230802.1-r0) (320/337) Installing abseil-cpp-stack-consumption (20230802.1-r0) (321/337) Installing abseil-cpp-string-view (20230802.1-r0) (322/337) Installing abseil-cpp-test-instance-tracker (20230802.1-r0) (323/337) Installing abseil-cpp-time-internal-test-util (20230802.1-r0) (324/337) Installing abseil-cpp-dev (20230802.1-r0) (325/337) Installing protobuf-dev (24.4-r1) (326/337) Installing libhistory (8.2.10-r0) (327/337) Installing readline-dev (8.2.10-r0) (328/337) Installing tzdata (2024a-r1) (329/337) Installing tcl (8.6.14-r1) (330/337) Installing tcl-dev (8.6.14-r1) (331/337) Installing iverilog (12.0-r3) (332/337) Installing .makedepends-yosys (20240619.151528) (333/337) Installing util-linux-openrc (2.40.1-r1) (334/337) Installing agetty-openrc (0.54-r2) (335/337) Installing perl-error (0.17029-r2) (336/337) Installing perl-git (2.45.2-r1) (337/337) Installing git-perl (2.45.2-r1) Executing busybox-1.36.1-r31.trigger Executing glib-2.80.3-r0.trigger No schema files found: doing nothing. OK: 917 MiB in 440 packages >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.42.tar.gz Connecting to distfiles.alpinelinux.org (172.105.82.32:443) wget: server returned error: HTTP/1.1 404 Not Found >>> yosys: Fetching https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.42.tar.gz Connecting to github.com (140.82.121.4:443) Connecting to codeload.github.com (140.82.121.9:443) saving to '/var/cache/distfiles/edge/yosys-0.42.tar.gz.part' yosys-0.42.tar.gz.pa 100% |********************************| 2741k 0:00:00 ETA '/var/cache/distfiles/edge/yosys-0.42.tar.gz.part' saved >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.42.tar.gz >>> yosys: Checking sha512sums... yosys-0.42.tar.gz: OK >>> yosys: Unpacking /var/cache/distfiles/edge/yosys-0.42.tar.gz... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 [ 0%] Building kernel/version_9b6afcf3f83.cc [ 0%] Building kernel/celltypes.pyh [ 0%] Building kernel/consteval.pyh [ 0%] Building kernel/log.pyh [ 0%] Building kernel/register.pyh [ 0%] Building kernel/rtlil.pyh [ 0%] Building kernel/sigtools.pyh [ 0%] Building kernel/yosys.pyh [ 0%] Building kernel/cost.pyh [ 0%] Building kernel/driver.o [ 0%] Building techlibs/common/simlib_help.inc [ 0%] Building techlibs/common/simcells_help.inc [ 1%] Building kernel/rtlil.o [ 1%] Building kernel/log.o [ 2%] Building kernel/calc.o [ 2%] Building kernel/yosys.o [ 2%] Building kernel/binding.o [ 3%] Building kernel/cellaigs.o [ 3%] Building kernel/celledges.o [ 3%] Building kernel/satgen.o [ 4%] Building kernel/scopeinfo.o [ 4%] Building kernel/qcsat.o [ 4%] Building kernel/mem.o [ 4%] Building kernel/ffmerge.o [ 5%] Building kernel/ff.o [ 5%] Building kernel/yw.o [ 5%] Building kernel/json.o [ 6%] Building kernel/fmt.o [ 6%] Building kernel/fstdata.o [ 6%] Building libs/bigint/BigIntegerAlgorithms.o [ 7%] Building libs/bigint/BigInteger.o [ 7%] Building libs/bigint/BigIntegerUtils.o [ 7%] Building libs/bigint/BigUnsigned.o [ 8%] Building libs/bigint/BigUnsignedInABase.o [ 8%] Building libs/sha1/sha1.o [ 8%] Building libs/json11/json11.o [ 8%] Building libs/ezsat/ezsat.o [ 9%] Building libs/ezsat/ezminisat.o [ 9%] Building libs/minisat/Options.o [ 9%] Building libs/minisat/SimpSolver.o [ 10%] Building libs/minisat/Solver.o [ 10%] Building libs/minisat/System.o [ 10%] Building libs/fst/fstapi.o [ 11%] Building libs/fst/fastlz.o [ 11%] Building libs/fst/lz4.o [ 11%] Building libs/subcircuit/subcircuit.o [ 12%] Building frontends/aiger/aigerparse.o [ 12%] Building frontends/ast/ast.o [ 12%] Building frontends/ast/simplify.o [ 12%] Building frontends/ast/genrtlil.o [ 13%] Building frontends/ast/dpicall.o [ 13%] Building frontends/ast/ast_binding.o [ 13%] Building frontends/blif/blifparse.o [ 14%] Building frontends/json/jsonparse.o [ 14%] Building frontends/liberty/liberty.o [ 14%] Building frontends/rpc/rpc_frontend.o [ 14%] Building frontends/rtlil/rtlil_parser.tab.cc [ 14%] Building frontends/rtlil/rtlil_lexer.cc [ 15%] Building frontends/rtlil/rtlil_frontend.o [ 16%] Building frontends/verific/verific.o [ 16%] Building frontends/verilog/verilog_parser.tab.cc [ 16%] Building frontends/verilog/preproc.o [ 17%] Building frontends/verilog/verilog_frontend.o [ 17%] Building frontends/verilog/const2ast.o [ 17%] Building passes/cmds/exec.o [ 18%] Building passes/cmds/add.o [ 18%] Building passes/cmds/delete.o [ 18%] Building passes/cmds/design.o [ 19%] Building passes/cmds/select.o [ 19%] Building passes/cmds/show.o [ 19%] Building passes/cmds/viz.o [ 20%] Building passes/cmds/rename.o [ 20%] Building passes/cmds/autoname.o [ 20%] Building passes/cmds/connect.o In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:119:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SimpSolver.cc:92:26: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 20%] Building passes/cmds/scatter.o [ 21%] Building passes/cmds/setundef.o [ 21%] Building passes/cmds/splitnets.o In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:119:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' libs/minisat/Solver.cc:134:19: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 21%] Building passes/cmds/splitcells.o [ 22%] Building passes/cmds/stat.o [ 22%] Building passes/cmds/setattr.o [ 22%] Building passes/cmds/copy.o [ 23%] Building passes/cmds/splice.o [ 23%] Building passes/cmds/scc.o [ 23%] Building passes/cmds/glift.o [ 24%] Building passes/cmds/torder.o [ 24%] Building passes/cmds/logcmd.o [ 24%] Building passes/cmds/tee.o [ 24%] Building passes/cmds/write_file.o [ 25%] Building passes/cmds/connwrappers.o [ 25%] Building passes/cmds/cover.o [ 25%] Building passes/cmds/trace.o [ 26%] Building passes/cmds/plugin.o [ 26%] Building passes/cmds/check.o [ 26%] Building passes/cmds/qwp.o [ 27%] Building passes/cmds/edgetypes.o [ 27%] Building passes/cmds/portlist.o [ 27%] Building passes/cmds/chformal.o [ 28%] Building passes/cmds/chtype.o [ 28%] Building passes/cmds/blackbox.o [ 28%] Building passes/cmds/ltp.o [ 28%] Building passes/cmds/bugpoint.o [ 29%] Building passes/cmds/scratchpad.o kernel/fmt.cc: In member function 'std::string Yosys::Fmt::render() const': kernel/fmt.cc:837:91: warning: comparison of integer expressions of different signedness: 'std::__cxx11::basic_string::size_type' {aka 'unsigned int'} and 'int' [-Wsign-compare] 837 | if (buf.size() % (group_size + 1) == group_size) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~ [ 29%] Building passes/cmds/logger.o [ 29%] Building passes/cmds/printattrs.o [ 30%] Building passes/cmds/sta.o [ 30%] Building passes/cmds/clean_zerowidth.o [ 30%] Building passes/cmds/xprop.o [ 31%] Building passes/cmds/dft_tag.o [ 31%] Building passes/cmds/future.o [ 31%] Building passes/cmds/box_derive.o [ 32%] Building passes/equiv/equiv_make.o [ 32%] Building passes/equiv/equiv_miter.o [ 32%] Building passes/equiv/equiv_simple.o [ 32%] Building passes/equiv/equiv_status.o [ 33%] Building passes/equiv/equiv_add.o [ 33%] Building passes/equiv/equiv_remove.o [ 33%] Building passes/equiv/equiv_induct.o [ 34%] Building passes/equiv/equiv_struct.o [ 34%] Building passes/equiv/equiv_purge.o [ 34%] Building passes/equiv/equiv_mark.o [ 35%] Building passes/equiv/equiv_opt.o [ 35%] Building passes/fsm/fsm.o [ 35%] Building passes/fsm/fsm_detect.o [ 36%] Building passes/fsm/fsm_extract.o [ 36%] Building passes/fsm/fsm_opt.o In file included from /usr/include/c++/13.2.1/bits/stl_algo.h:61, from /usr/include/c++/13.2.1/algorithm:61, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:42, from passes/cmds/qwp.cc:20: /usr/include/c++/13.2.1/bits/stl_heap.h: In function 'void std::__adjust_heap(_RandomAccessIterator, _Distance, _Distance, _Tp, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Distance = int; _Tp = pair; _Compare = __gnu_cxx::__ops::_Iter_less_iter]': /usr/include/c++/13.2.1/bits/stl_heap.h:224:5: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 224 | __adjust_heap(_RandomAccessIterator __first, _Distance __holeIndex, | ^~~~~~~~~~~~~ [ 36%] Building passes/fsm/fsm_expand.o In file included from /usr/include/c++/13.2.1/vector:72, from ./kernel/yosys_common.h:26: /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {const {anonymous}::QwpWorker::Node&}; _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector<{anonymous}::QwpWorker::Node>::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ In file included from /usr/include/c++/13.2.1/vector:66: /usr/include/c++/13.2.1/bits/stl_vector.h: In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]': /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::QwpWorker::Node*, std::vector<{anonymous}::QwpWorker::Node> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 36%] Building passes/fsm/fsm_recode.o /usr/include/c++/13.2.1/bits/stl_algo.h: In function 'void std::__introsort_loop(_RandomAccessIterator, _RandomAccessIterator, _Size, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Size = int; _Compare = __gnu_cxx::__ops::_Iter_less_iter]': /usr/include/c++/13.2.1/bits/stl_algo.h:1918:5: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1918 | __introsort_loop(_RandomAccessIterator __first, | ^~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_algo.h:1918:5: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 /usr/include/c++/13.2.1/bits/stl_algo.h:1932:32: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1932 | std::__introsort_loop(__cut, __last, __depth_limit, __comp); | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_algo.h: In function 'void std::__insertion_sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Compare = __gnu_cxx::__ops::_Iter_less_iter]': /usr/include/c++/13.2.1/bits/stl_algo.h:1812:5: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1812 | __insertion_sort(_RandomAccessIterator __first, | ^~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_algo.h:1812:5: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 [ 37%] Building passes/fsm/fsm_info.o [ 37%] Building passes/fsm/fsm_export.o [ 37%] Building passes/fsm/fsm_map.o [ 38%] Building passes/hierarchy/hierarchy.o /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {const double&}; _Tp = double; _Alloc = std::allocator]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair}; _Tp = std::pair; _Alloc = std::allocator >]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector >::iterator' changed in GCC 7.1 [ 38%] Building passes/hierarchy/uniquify.o [ 38%] Building passes/hierarchy/submod.o [ 39%] Building passes/memory/memory.o [ 39%] Building passes/memory/memory_dff.o [ 39%] Building passes/memory/memory_share.o [ 40%] Building passes/memory/memory_collect.o [ 40%] Building passes/memory/memory_unpack.o [ 40%] Building passes/memory/memory_bram.o [ 40%] Building passes/memory/memory_map.o [ 41%] Building passes/memory/memory_memx.o [ 41%] Building passes/memory/memory_nordff.o /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, int}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, int&}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, int}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = Yosys::RTLIL::Wire*; T = double; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:365:24, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = double; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:619:17: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, int&}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = Yosys::RTLIL::Wire*; T = double; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:369:24, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = double; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:619:17: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [ 41%] Building passes/memory/memory_narrow.o [ 42%] Building passes/memory/memory_libmap.o /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, double>, int}; _Tp = Yosys::hashlib::dict, double>::entry_t; _Alloc = std::allocator, double>::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector, double>::entry_t, std::allocator, double>::entry_t> >::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ [ 42%] Building passes/memory/memory_bmux2rom.o /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, double>, int&}; _Tp = Yosys::hashlib::dict, double>::entry_t; _Alloc = std::allocator, double>::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector, double>::entry_t, std::allocator, double>::entry_t> >::iterator' changed in GCC 7.1 In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, double>, int}; _Tp = Yosys::hashlib::dict, double>::entry_t; _Alloc = std::allocator, double>::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = std::pair; T = double; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:365:24, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = std::pair; T = double; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:619:17: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator, double>::entry_t*, std::vector, double>::entry_t, std::allocator, double>::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, double>, int&}; _Tp = Yosys::hashlib::dict, double>::entry_t; _Alloc = std::allocator, double>::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = std::pair; T = double; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:369:24, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = std::pair; T = double; OPS = Yosys::hashlib::hash_ops >]' at ./kernel/hashlib.h:619:17: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator, double>::entry_t*, std::vector, double>::entry_t, std::allocator, double>::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [ 42%] Building passes/memory/memlib.o [ 43%] Building passes/opt/opt.o [ 43%] Building passes/opt/opt_merge.o [ 43%] Building passes/opt/opt_mem.o [ 44%] Building passes/opt/opt_mem_feedback.o [ 44%] Building passes/opt/opt_mem_priority.o [ 44%] Building passes/opt/opt_mem_widen.o In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair}; _Tp = std::pair; _Alloc = std::allocator >]', inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = std::pair; _Alloc = std::allocator >]' at /usr/include/c++/13.2.1/bits/stl_vector.h:1296:21, inlined from 'void {anonymous}::QwpWorker::run_worker(int)' at passes/cmds/qwp.cc:524:25: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In function 'void std::__sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Compare = __gnu_cxx::__ops::_Iter_less_iter]', inlined from 'void std::sort(_RAIter, _RAIter) [with _RAIter = __gnu_cxx::__normal_iterator*, vector > >]' at /usr/include/c++/13.2.1/bits/stl_algo.h:4861:18, inlined from 'void {anonymous}::QwpWorker::run_worker(int)' at passes/cmds/qwp.cc:526:12: /usr/include/c++/13.2.1/bits/stl_algo.h:1947:32: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1947 | std::__introsort_loop(__first, __last, | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ 1948 | std::__lg(__last - __first) * 2, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1949 | __comp); | ~~~~~~~ In function 'void std::__final_insertion_sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Compare = __gnu_cxx::__ops::_Iter_less_iter]', inlined from 'void std::__sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = __gnu_cxx::__normal_iterator*, vector > >; _Compare = __gnu_cxx::__ops::_Iter_less_iter]' at /usr/include/c++/13.2.1/bits/stl_algo.h:1950:31, inlined from 'void std::sort(_RAIter, _RAIter) [with _RAIter = __gnu_cxx::__normal_iterator*, vector > >]' at /usr/include/c++/13.2.1/bits/stl_algo.h:4861:18, inlined from 'void {anonymous}::QwpWorker::run_worker(int)' at passes/cmds/qwp.cc:526:12: /usr/include/c++/13.2.1/bits/stl_algo.h:1859:32: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1859 | std::__insertion_sort(__first, __first + int(_S_threshold), __comp); | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_algo.h:1864:30: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator*, std::vector > >' changed in GCC 7.1 1864 | std::__insertion_sort(__first, __last, __comp); | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]', inlined from 'void {anonymous}::QwpWorker::run_worker(int)' at passes/cmds/qwp.cc:592:33: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::QwpWorker::Node*, std::vector<{anonymous}::QwpWorker::Node> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 45%] Building passes/opt/opt_muxtree.o [ 45%] Building passes/opt/opt_reduce.o [ 45%] Building passes/opt/opt_dff.o [ 45%] Building passes/opt/opt_share.o [ 46%] Building passes/opt/opt_clean.o [ 46%] Building passes/opt/opt_expr.o [ 46%] Building passes/opt/share.o [ 47%] Building passes/opt/wreduce.o [ 47%] Building passes/opt/opt_demorgan.o [ 47%] Building passes/opt/rmports.o [ 48%] Building passes/opt/opt_lut.o [ 48%] Building passes/opt/opt_lut_ins.o [ 48%] Building passes/opt/opt_ffinv.o [ 49%] Building passes/opt/pmux2shiftx.o [ 49%] Building passes/opt/muxpack.o [ 49%] Building passes/pmgen/test_pmgen_pm.h [ 49%] Building passes/pmgen/ice40_dsp_pm.h [ 49%] Building passes/pmgen/peepopt_pm.h [ 49%] Building passes/pmgen/xilinx_srl_pm.h [ 49%] Building passes/pmgen/ice40_wrapcarry_pm.h [ 49%] Building passes/pmgen/xilinx_dsp_pm.h [ 49%] Building passes/pmgen/xilinx_dsp48a_pm.h [ 49%] Building passes/pmgen/xilinx_dsp_CREG_pm.h [ 49%] Building passes/pmgen/xilinx_dsp_cascade_pm.h [ 50%] Building passes/pmgen/peepopt.o [ 51%] Building passes/pmgen/xilinx_srl.o [ 51%] Building passes/proc/proc.o [ 51%] Building passes/proc/proc_prune.o [ 52%] Building passes/proc/proc_clean.o In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {{anonymous}::QwpWorker::Node}; _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]', inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]' at /usr/include/c++/13.2.1/bits/stl_vector.h:1296:21, inlined from 'void {anonymous}::QwpWorker::load_module()' at passes/cmds/qwp.cc:159:20: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::QwpWorker::Node*, std::vector<{anonymous}::QwpWorker::Node> >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {{anonymous}::QwpWorker::Node}; _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]', inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = {anonymous}::QwpWorker::Node; _Alloc = std::allocator<{anonymous}::QwpWorker::Node>]' at /usr/include/c++/13.2.1/bits/stl_vector.h:1296:21, inlined from 'void {anonymous}::QwpWorker::load_module()' at passes/cmds/qwp.cc:184:19: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::QwpWorker::Node*, std::vector<{anonymous}::QwpWorker::Node> >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [ 52%] Building passes/proc/proc_rmdead.o [ 52%] Building passes/proc/proc_init.o [ 53%] Building passes/proc/proc_arst.o [ 53%] Building passes/proc/proc_rom.o [ 53%] Building passes/proc/proc_mux.o [ 53%] Building passes/proc/proc_dlatch.o [ 54%] Building passes/proc/proc_dff.o [ 54%] Building passes/proc/proc_memwr.o [ 54%] Building passes/sat/sat.o [ 55%] Building passes/sat/freduce.o [ 55%] Building passes/sat/eval.o In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = double; _Alloc = std::allocator]', inlined from 'void {anonymous}::QwpWorker::run()' at passes/cmds/qwp.cc:756:26, inlined from 'virtual void {anonymous}::QwpPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/cmds/qwp.cc:848:14: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = double; _Alloc = std::allocator]', inlined from 'void {anonymous}::QwpWorker::run()' at passes/cmds/qwp.cc:757:35, inlined from 'virtual void {anonymous}::QwpPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/cmds/qwp.cc:848:14: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 55%] Building passes/sat/sim.o [ 56%] Building passes/sat/miter.o [ 56%] Building passes/sat/expose.o [ 56%] Building passes/sat/assertpmux.o [ 57%] Building passes/sat/clk2fflogic.o [ 57%] Building passes/sat/async2sync.o [ 57%] Building passes/sat/formalff.o [ 57%] Building passes/sat/supercover.o [ 58%] Building passes/sat/fmcombine.o [ 58%] Building passes/sat/mutate.o [ 58%] Building passes/sat/cutpoint.o [ 59%] Building passes/sat/fminit.o [ 59%] Building passes/sat/recover_names.o [ 59%] Building passes/sat/qbfsat.o [ 60%] Building passes/sat/synthprop.o [ 60%] Building passes/techmap/flatten.o [ 60%] Building passes/techmap/techmap.o [ 61%] Building passes/techmap/simplemap.o [ 61%] Building passes/techmap/dfflibmap.o [ 61%] Building passes/techmap/maccmap.o In file included from /usr/include/c++/13.2.1/vector:72, from passes/memory/memlib.h:24, from passes/memory/memory_libmap.cc:20: /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {const {anonymous}::MemConfig&}; _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector<{anonymous}::MemConfig>::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ [ 61%] Building passes/techmap/booth.o In file included from /usr/include/c++/13.2.1/vector:72, from ./kernel/yosys_common.h:26, from ./kernel/register.h:23, from passes/opt/opt_merge.cc:20: /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, int}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {std::pair, int&}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 In file included from /usr/include/c++/13.2.1/vector:72, from passes/memory/memlib.h:24, from passes/memory/memlib.cc:20: /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {const Yosys::MemLibrary::Ram&}; _Tp = Yosys::MemLibrary::Ram; _Alloc = std::allocator]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ [ 62%] Building passes/techmap/libparse.o [ 62%] Building passes/techmap/abc.o In file included from /usr/include/c++/13.2.1/vector:66: In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::assign_wr_ports()' at passes/memory/memory_libmap.cc:732:24: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 62%] Building passes/techmap/abc9.o [ 63%] Building passes/techmap/abc9_exe.o In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:907:22: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:915:23: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:940:24: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:944:24: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:953:24: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:979:25: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::handle_trans()' at passes/memory/memory_libmap.cc:987:25: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 63%] Building passes/techmap/abc9_ops.o [ 63%] Building passes/techmap/iopadmap.o [ 64%] Building passes/techmap/clkbufmap.o [ 64%] Building passes/techmap/hilomap.o [ 64%] Building passes/techmap/extract.o [ 65%] Building passes/techmap/extract_fa.o [ 65%] Building passes/techmap/extract_counter.o [ 65%] Building passes/techmap/extract_reduce.o [ 65%] Building passes/techmap/alumacc.o [ 66%] Building passes/techmap/dffinit.o [ 66%] Building passes/techmap/pmuxtree.o [ 66%] Building passes/techmap/bmuxmap.o [ 67%] Building passes/techmap/demuxmap.o [ 67%] Building passes/techmap/bwmuxmap.o [ 67%] Building passes/techmap/muxcover.o [ 68%] Building passes/techmap/aigmap.o [ 68%] Building passes/techmap/tribuf.o [ 68%] Building passes/techmap/lut2mux.o [ 69%] Building passes/techmap/nlutmap.o [ 69%] Building passes/techmap/shregmap.o [ 69%] Building passes/techmap/deminout.o [ 69%] Building passes/techmap/insbuf.o [ 70%] Building passes/techmap/attrmvcp.o [ 70%] Building passes/techmap/attrmap.o [ 70%] Building passes/techmap/zinit.o In file included from /usr/include/c++/13.2.1/vector:66: In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = Yosys::MemLibrary::Ram; _Alloc = std::allocator]', inlined from 'void {anonymous}::Parser::compile_ram(int)' at passes/memory/memlib.cc:1026:22, inlined from 'void {anonymous}::Parser::parse_top_item()' at passes/memory/memlib.cc:795:16: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::assign_rd_ports()' at passes/memory/memory_libmap.cc:799:24: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::assign_rd_ports()' at passes/memory/memory_libmap.cc:894:23: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 71%] Building passes/techmap/dfflegalize.o [ 71%] Building passes/techmap/dffunmap.o [ 71%] Building passes/techmap/flowmap.o [ 72%] Building passes/techmap/extractinv.o [ 72%] Building passes/techmap/cellmatch.o [ 72%] Building passes/tests/test_autotb.o [ 73%] Building passes/tests/test_cell.o [ 73%] Building passes/tests/test_abcloop.o [ 73%] Building backends/aiger/aiger.o [ 73%] Building backends/aiger/xaiger.o [ 74%] Building backends/blif/blif.o [ 74%] Building backends/btor/btor.o [ 74%] Building backends/cxxrtl/cxxrtl_backend.o [ 75%] Building backends/edif/edif.o [ 75%] Building backends/firrtl/firrtl.o [ 75%] Building backends/intersynth/intersynth.o [ 76%] Building backends/jny/jny.o [ 76%] Building backends/json/json.o [ 76%] Building backends/rtlil/rtlil_backend.o [ 77%] Building backends/simplec/simplec.o [ 77%] Building backends/smt2/smt2.o [ 77%] Building backends/smv/smv.o [ 77%] Building backends/spice/spice.o [ 78%] Building backends/table/table.o [ 78%] Building backends/verilog/verilog_backend.o [ 78%] Building techlibs/achronix/synth_achronix.o [ 79%] Building techlibs/anlogic/synth_anlogic.o [ 79%] Building techlibs/anlogic/anlogic_eqn.o [ 79%] Building techlibs/anlogic/anlogic_fixcarry.o [ 80%] Building techlibs/common/synth.o [ 80%] Building techlibs/common/prep.o [ 80%] Building techlibs/coolrunner2/synth_coolrunner2.o [ 81%] Building techlibs/coolrunner2/coolrunner2_sop.o [ 81%] Building techlibs/coolrunner2/coolrunner2_fixup.o [ 81%] Building techlibs/easic/synth_easic.o [ 81%] Building techlibs/ecp5/synth_ecp5.o In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from '{anonymous}::MemMapping::MemMapping({anonymous}::MapWorker&, Yosys::Mem&, const Yosys::MemLibrary::Library&, const {anonymous}::PassOptions&)' at passes/memory/memory_libmap.cc:217:18: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = {anonymous}::MemConfig; _Alloc = std::allocator<{anonymous}::MemConfig>]', inlined from 'void {anonymous}::MemMapping::prune_post_geom()' at passes/memory/memory_libmap.cc:1511:22, inlined from '{anonymous}::MemMapping::MemMapping({anonymous}::MapWorker&, Yosys::Mem&, const Yosys::MemLibrary::Library&, const {anonymous}::PassOptions&)' at passes/memory/memory_libmap.cc:230:18: /usr/include/c++/13.2.1/bits/stl_vector.h:1289:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator<{anonymous}::MemConfig*, std::vector<{anonymous}::MemConfig> >' changed in GCC 7.1 1289 | _M_realloc_insert(end(), __x); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ [ 82%] Building techlibs/efinix/synth_efinix.o [ 82%] Building techlibs/efinix/efinix_fixcarry.o [ 82%] Building techlibs/fabulous/synth_fabulous.o [ 83%] Building techlibs/gatemate/synth_gatemate.o [ 83%] Building techlibs/gatemate/gatemate_foldinv.o [ 83%] Building techlibs/gowin/synth_gowin.o [ 84%] Building techlibs/greenpak4/synth_greenpak4.o [ 84%] Building techlibs/greenpak4/greenpak4_dffinv.o [ 84%] Building techlibs/ice40/synth_ice40.o [ 85%] Building techlibs/ice40/ice40_braminit.o [ 85%] Building techlibs/ice40/ice40_opt.o [ 85%] Building techlibs/intel/synth_intel.o [ 85%] Building techlibs/intel_alm/synth_intel_alm.o [ 86%] Building techlibs/lattice/synth_lattice.o [ 86%] Building techlibs/lattice/lattice_gsr.o [ 86%] Building techlibs/nexus/synth_nexus.o [ 87%] Building techlibs/quicklogic/synth_quicklogic.o [ 87%] Building techlibs/quicklogic/ql_bram_merge.o [ 87%] Building techlibs/quicklogic/ql_bram_types.o [ 88%] Building techlibs/quicklogic/ql_dsp_simd.o [ 88%] Building techlibs/quicklogic/ql_dsp_io_regs.o [ 88%] Building techlibs/quicklogic/ql_dsp_macc_pm.h [ 89%] Building techlibs/sf2/synth_sf2.o [ 89%] Building techlibs/xilinx/synth_xilinx.o [ 89%] Building techlibs/xilinx/xilinx_dffopt.o [ 99%] Building yosys-config [ 99%] Building passes/techmap/filterlib.o [ 99%] Building yosys-smtbmc [ 99%] Building yosys-witness [ 99%] Building share/include/kernel/binding.h [ 99%] Building share/include/kernel/cellaigs.h [ 99%] Building share/include/kernel/celledges.h [ 99%] Building share/include/kernel/celltypes.h [ 99%] Building share/include/kernel/consteval.h [ 99%] Building share/include/kernel/constids.inc In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, int}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = long long unsigned int; T = Yosys::RTLIL::Cell*; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:365:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(std::pair<_T1, _T2>&&) [with K = long long unsigned int; T = Yosys::RTLIL::Cell*; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:497:16, inlined from '{anonymous}::OptMergeWorker::OptMergeWorker(Yosys::RTLIL::Design*, Yosys::RTLIL::Module*, bool, bool, bool)' at passes/opt/opt_merge.cc:279:29, inlined from 'virtual void {anonymous}::OptMergePass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/opt/opt_merge.cc:366:81: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::pair, int&}; _Tp = Yosys::hashlib::dict::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::dict::do_insert(std::pair<_T1, _T2>&&, int&) [with K = long long unsigned int; T = Yosys::RTLIL::Cell*; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:369:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(std::pair<_T1, _T2>&&) [with K = long long unsigned int; T = Yosys::RTLIL::Cell*; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:497:16, inlined from '{anonymous}::OptMergeWorker::OptMergeWorker(Yosys::RTLIL::Design*, Yosys::RTLIL::Module*, bool, bool, bool)' at passes/opt/opt_merge.cc:279:29, inlined from 'virtual void {anonymous}::OptMergePass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/opt/opt_merge.cc:366:81: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [ 99%] Building share/include/kernel/cost.h [ 99%] Building share/include/kernel/ff.h [ 99%] Building share/include/kernel/ffinit.h [ 99%] Building share/include/kernel/ffmerge.h [ 99%] Building share/include/kernel/fmt.h [ 99%] Building share/include/kernel/fstdata.h [ 99%] Building share/include/kernel/hashlib.h [ 99%] Building share/include/kernel/json.h [ 99%] Building share/include/kernel/log.h [ 99%] Building share/include/kernel/macc.h [ 99%] Building share/include/kernel/modtools.h [ 99%] Building share/include/kernel/mem.h [ 99%] Building share/include/kernel/qcsat.h [ 99%] Building share/include/kernel/register.h [ 99%] Building share/include/kernel/rtlil.h [ 99%] Building share/include/kernel/satgen.h [ 99%] Building share/include/kernel/scopeinfo.h [ 99%] Building share/include/kernel/sigtools.h [ 99%] Building share/include/kernel/timinginfo.h [ 99%] Building share/include/kernel/utils.h [ 99%] Building share/include/kernel/yosys.h [ 99%] Building share/include/kernel/yosys_common.h [ 99%] Building share/include/kernel/yw.h [ 99%] Building share/include/libs/ezsat/ezsat.h [ 99%] Building share/include/libs/ezsat/ezminisat.h [ 99%] Building share/include/libs/fst/fstapi.h [ 99%] Building share/include/libs/sha1/sha1.h [ 99%] Building share/include/libs/json11/json11.hpp [ 99%] Building share/include/passes/fsm/fsmdata.h [ 99%] Building share/include/frontends/ast/ast.h [ 99%] Building share/include/frontends/ast/ast_binding.h [ 99%] Building share/include/frontends/blif/blifparse.h [ 99%] Building share/include/backends/rtlil/rtlil_backend.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc [ 99%] Building share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h [ 99%] Building share/python3/smtio.py [ 99%] Building share/python3/ywio.py [ 99%] Building share/achronix/speedster22i/cells_sim.v [ 99%] Building share/achronix/speedster22i/cells_map.v [ 99%] Building share/anlogic/cells_map.v [ 99%] Building share/anlogic/arith_map.v [ 99%] Building share/anlogic/cells_sim.v [ 99%] Building share/anlogic/eagle_bb.v [ 99%] Building share/anlogic/lutrams.txt [ 99%] Building share/anlogic/lutrams_map.v [ 99%] Building share/anlogic/brams.txt [ 99%] Building share/anlogic/brams_map.v [ 99%] Building share/simlib.v [ 99%] Building share/simcells.v [ 99%] Building share/techmap.v [ 99%] Building share/smtmap.v [ 99%] Building share/pmux2mux.v [ 99%] Building share/adff2dff.v [ 99%] Building share/dff2ff.v [ 99%] Building share/gate2lut.v [ 99%] Building share/cmp2lut.v [ 99%] Building share/cells.lib [ 99%] Building share/mul2dsp.v [ 99%] Building share/abc9_model.v [ 99%] Building share/abc9_map.v [ 99%] Building share/abc9_unmap.v [ 99%] Building share/cmp2lcu.v [ 99%] Building share/cmp2softlogic.v In file included from /usr/include/c++/13.2.1/vector:72, from ./kernel/yosys_common.h:26, from ./kernel/yosys.h:42, from ./kernel/celltypes.h:23, from passes/techmap/cellmatch.cc:1: /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {long long unsigned int, int}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 445 | vector<_Tp, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~ [ 99%] Building share/choices/kogge-stone.v [ 99%] Building share/coolrunner2/cells_latch.v [ 99%] Building share/coolrunner2/cells_sim.v [ 99%] Building share/coolrunner2/cells_counter_map.v [ 99%] Building share/coolrunner2/tff_extract.v /usr/include/c++/13.2.1/bits/vector.tcc: In member function 'void std::vector<_Tp, _Alloc>::_M_realloc_insert(iterator, _Args&& ...) [with _Args = {long long unsigned int, int&}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]': /usr/include/c++/13.2.1/bits/vector.tcc:445:7: note: parameter passing for argument of type 'std::vector::entry_t, std::allocator::entry_t> >::iterator' changed in GCC 7.1 [ 99%] Building share/coolrunner2/xc2_dff.lib [ 99%] Building share/ecp5/cells_ff.vh [ 99%] Building share/ecp5/cells_io.vh [ 99%] Building share/ecp5/cells_map.v [ 99%] Building share/ecp5/cells_sim.v [ 99%] Building share/ecp5/cells_bb.v [ 99%] Building share/ecp5/lutrams_map.v [ 99%] Building share/ecp5/lutrams.txt [ 99%] Building share/ecp5/brams_map.v [ 99%] Building share/ecp5/brams.txt [ 99%] Building share/ecp5/arith_map.v [ 99%] Building share/ecp5/latches_map.v [ 99%] Building share/ecp5/dsp_map.v [ 99%] Building share/efinix/cells_map.v [ 99%] Building share/efinix/arith_map.v [ 99%] Building share/efinix/cells_sim.v [ 99%] Building share/efinix/brams_map.v [ 99%] Building share/efinix/gbuf_map.v [ 99%] Building share/efinix/brams.txt [ 99%] Building share/fabulous/cells_map.v [ 99%] Building share/fabulous/prims.v [ 99%] Building share/fabulous/latches_map.v [ 99%] Building share/fabulous/ff_map.v [ 99%] Building share/fabulous/ram_regfile.txt [ 99%] Building share/fabulous/regfile_map.v [ 99%] Building share/fabulous/io_map.v [ 99%] Building share/fabulous/arith_map.v [ 99%] Building share/gatemate/reg_map.v [ 99%] Building share/gatemate/mux_map.v [ 99%] Building share/gatemate/lut_map.v [ 99%] Building share/gatemate/mul_map.v [ 99%] Building share/gatemate/arith_map.v [ 99%] Building share/gatemate/cells_sim.v [ 99%] Building share/gatemate/cells_bb.v [ 99%] Building share/gatemate/brams_map.v [ 99%] Building share/gatemate/brams.txt [ 99%] Building share/gatemate/brams_init_20.vh [ 99%] Building share/gatemate/brams_init_40.vh [ 99%] Building share/gatemate/inv_map.v [ 99%] Building techlibs/gatemate/lut_tree_lib.mk [ 99%] Building share/gowin/cells_map.v [ 99%] Building share/gowin/cells_sim.v [ 99%] Building share/gowin/cells_xtra.v [ 99%] Building share/gowin/arith_map.v [ 99%] Building share/gowin/brams_map.v [ 99%] Building share/gowin/brams.txt [ 99%] Building share/gowin/lutrams_map.v [ 99%] Building share/gowin/lutrams.txt [ 99%] Building share/greenpak4/cells_blackbox.v [ 99%] Building share/greenpak4/cells_latch.v [ 99%] Building share/greenpak4/cells_map.v [ 99%] Building share/greenpak4/cells_sim.v [ 99%] Building share/greenpak4/cells_sim_ams.v [ 99%] Building share/greenpak4/cells_sim_digital.v [ 99%] Building share/greenpak4/cells_sim_wip.v [ 99%] Building share/greenpak4/gp_dff.lib [ 99%] Building share/ice40/arith_map.v [ 99%] Building share/ice40/cells_map.v [ 99%] Building share/ice40/ff_map.v [ 99%] Building share/ice40/cells_sim.v [ 99%] Building share/ice40/latches_map.v [ 99%] Building share/ice40/brams.txt [ 99%] Building share/ice40/brams_map.v [ 99%] Building share/ice40/spram.txt [ 99%] Building share/ice40/spram_map.v [ 99%] Building share/ice40/dsp_map.v [ 99%] Building share/ice40/abc9_model.v [ 99%] Building share/intel/common/m9k_bb.v [ 99%] Building share/intel/common/altpll_bb.v [ 99%] Building share/intel/common/brams_m9k.txt [ 99%] Building share/intel/common/brams_map_m9k.v [ 99%] Building share/intel/common/ff_map.v [ 99%] Building share/intel/max10/cells_sim.v [ 99%] Building share/intel/cyclone10lp/cells_sim.v [ 99%] Building share/intel/cycloneiv/cells_sim.v [ 99%] Building share/intel/cycloneive/cells_sim.v [ 99%] Building share/intel/max10/cells_map.v [ 99%] Building share/intel/cyclone10lp/cells_map.v [ 99%] Building share/intel/cycloneiv/cells_map.v [ 99%] Building share/intel/cycloneive/cells_map.v [ 99%] Building share/intel_alm/common/abc9_map.v [ 99%] Building share/intel_alm/common/abc9_unmap.v [ 99%] Building share/intel_alm/common/abc9_model.v [ 99%] Building share/intel_alm/common/alm_map.v [ 99%] Building share/intel_alm/common/alm_sim.v [ 99%] Building share/intel_alm/common/arith_alm_map.v [ 99%] Building share/intel_alm/common/dff_map.v [ 99%] Building share/intel_alm/common/dff_sim.v [ 99%] Building share/intel_alm/common/dsp_sim.v [ 99%] Building share/intel_alm/common/dsp_map.v [ 99%] Building share/intel_alm/common/mem_sim.v [ 99%] Building share/intel_alm/common/misc_sim.v [ 99%] Building share/intel_alm/cyclonev/cells_sim.v [ 99%] Building share/intel_alm/common/bram_m10k.txt [ 99%] Building share/intel_alm/common/bram_m10k_map.v [ 99%] Building share/intel_alm/common/lutram_mlab.txt [ 99%] Building share/intel_alm/common/megafunction_bb.v [ 99%] Building share/lattice/cells_ff.vh [ 99%] Building share/lattice/cells_io.vh [ 99%] Building share/lattice/cells_map.v [ 99%] Building share/lattice/common_sim.vh [ 99%] Building share/lattice/ccu2d_sim.vh [ 99%] Building share/lattice/ccu2c_sim.vh [ 99%] Building share/lattice/cells_sim_ecp5.v [ 99%] Building share/lattice/cells_sim_xo2.v kernel/satgen.cc: In member function 'bool Yosys::SatGen::importCell(Yosys::RTLIL::Cell*, int)': kernel/satgen.cc:1240:67: warning: 'undef_srst' may be used uninitialized [-Wmaybe-uninitialized] 1240 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1231:37: note: 'undef_srst' was declared here 1231 | int undef_srst; | ^~~~~~~~~~ kernel/satgen.cc:1254:67: warning: 'undef_ce' may be used uninitialized [-Wmaybe-uninitialized] 1254 | std::tie(d, undef_d) = mux(ce, undef_ce, d, undef_d, old_q, undef_old_q); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1245:37: note: 'undef_ce' was declared here 1245 | int undef_ce; | ^~~~~~~~ kernel/satgen.cc:1268:67: warning: 'undef_srst' may be used uninitialized [-Wmaybe-uninitialized] 1268 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1259:37: note: 'undef_srst' was declared here 1259 | int undef_srst; | ^~~~~~~~~~ [ 99%] Building share/lattice/cells_sim_xo3.v [ 99%] Building share/lattice/cells_sim_xo3d.v [ 99%] Building share/lattice/cells_bb_ecp5.v [ 99%] Building share/lattice/cells_bb_xo2.v [ 99%] Building share/lattice/cells_bb_xo3.v [ 99%] Building share/lattice/cells_bb_xo3d.v [ 99%] Building share/lattice/lutrams_map.v [ 99%] Building share/lattice/lutrams.txt [ 99%] Building share/lattice/brams_map_16kd.v [ 99%] Building share/lattice/brams_16kd.txt [ 99%] Building share/lattice/brams_map_8kc.v [ 99%] Building share/lattice/brams_8kc.txt [ 99%] Building share/lattice/arith_map_ccu2c.v [ 99%] Building share/lattice/arith_map_ccu2d.v [ 99%] Building share/lattice/latches_map.v [ 99%] Building share/lattice/dsp_map_18x18.v [ 99%] Building share/nexus/cells_map.v [ 99%] Building share/nexus/cells_sim.v [ 99%] Building share/nexus/parse_init.vh [ 99%] Building share/nexus/cells_xtra.v [ 99%] Building share/nexus/lutrams_map.v [ 99%] Building share/nexus/lutrams.txt [ 99%] Building share/nexus/brams_map.v [ 99%] Building share/nexus/brams.txt [ 99%] Building share/nexus/lrams_map.v [ 99%] Building share/nexus/lrams.txt [ 99%] Building share/nexus/arith_map.v [ 99%] Building share/nexus/latches_map.v [ 99%] Building share/nexus/dsp_map.v [ 99%] Building share/quicklogic/common/cells_sim.v [ 99%] Building share/quicklogic/pp3/ffs_map.v [ 99%] Building share/quicklogic/pp3/lut_map.v [ 99%] Building share/quicklogic/pp3/latches_map.v [ 99%] Building share/quicklogic/pp3/cells_map.v [ 99%] Building share/quicklogic/pp3/cells_sim.v [ 99%] Building share/quicklogic/pp3/abc9_model.v [ 99%] Building share/quicklogic/pp3/abc9_map.v [ 99%] Building share/quicklogic/pp3/abc9_unmap.v [ 99%] Building share/quicklogic/qlf_k6n10f/arith_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/libmap_brams.txt [ 99%] Building share/quicklogic/qlf_k6n10f/libmap_brams_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/brams_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/brams_sim.v [ 99%] Building techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/cells_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/ffs_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_sim.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/dsp_final_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v [ 99%] Building share/quicklogic/qlf_k6n10f/ufifo_ctl.v [ 99%] Building share/quicklogic/qlf_k6n10f/sram1024x18_mem.v [ 99%] Building share/sf2/arith_map.v [ 99%] Building share/sf2/cells_map.v [ 99%] Building share/sf2/cells_sim.v [ 99%] Building share/xilinx/cells_map.v [ 99%] Building share/xilinx/cells_sim.v [ 99%] Building share/xilinx/cells_xtra.v [ 99%] Building share/xilinx/lutrams_xcv.txt [ 99%] Building share/xilinx/lutrams_xcv_map.v [ 99%] Building share/xilinx/lutrams_xc5v.txt [ 99%] Building share/xilinx/lutrams_xcu.txt [ 99%] Building share/xilinx/lutrams_xc5v_map.v [ 99%] Building share/xilinx/brams_xcv.txt [ 99%] Building share/xilinx/brams_xcv_map.v [ 99%] Building share/xilinx/brams_defs.vh [ 99%] Building share/xilinx/brams_xc2v.txt [ 99%] Building share/xilinx/brams_xc2v_map.v [ 99%] Building share/xilinx/brams_xc3sda.txt [ 99%] Building share/xilinx/brams_xc3sda_map.v [ 99%] Building share/xilinx/brams_xc4v.txt [ 99%] Building share/xilinx/brams_xc4v_map.v [ 99%] Building share/xilinx/brams_xc5v_map.v [ 99%] Building share/xilinx/brams_xc6v_map.v [ 99%] Building share/xilinx/brams_xcu_map.v [ 99%] Building share/xilinx/urams.txt [ 99%] Building share/xilinx/urams_map.v [ 99%] Building share/xilinx/arith_map.v [ 99%] Building share/xilinx/ff_map.v [ 99%] Building share/xilinx/lut_map.v [ 99%] Building share/xilinx/mux_map.v [ 99%] Building share/xilinx/xc3s_mult_map.v [ 99%] Building share/xilinx/xc3sda_dsp_map.v [ 99%] Building share/xilinx/xc6s_dsp_map.v [ 99%] Building share/xilinx/xc4v_dsp_map.v [ 99%] Building share/xilinx/xc5v_dsp_map.v [ 99%] Building share/xilinx/xc7_dsp_map.v [ 99%] Building share/xilinx/xcu_dsp_map.v [ 99%] Building share/xilinx/abc9_model.v [ 99%] Building kernel/version_9b6afcf3f83.o [ 99%] Building kernel/python_wrappers.cc [ 99%] Building kernel/register.o [ 99%] Building frontends/rtlil/rtlil_parser.tab.o [ 99%] Building frontends/rtlil/rtlil_lexer.o [ 99%] Building frontends/verilog/verilog_parser.tab.o [ 99%] Building frontends/verilog/verilog_lexer.cc [ 99%] Building passes/pmgen/test_pmgen.o [ 99%] Building passes/pmgen/ice40_dsp.o [ 99%] Building passes/pmgen/ice40_wrapcarry.o [ 99%] Building passes/pmgen/xilinx_dsp.o [ 99%] Building techlibs/quicklogic/ql_dsp_macc.o [ 99%] Building yosys-filterlib [ 99%] Building share/gatemate/lut_tree_cells.genlib [ 99%] Building share/gatemate/lut_tree_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/bram_types_sim.v [ 99%] Building frontends/verilog/verilog_lexer.o In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {long long unsigned int, int}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::pool::do_insert(K&&, int&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:804:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::pool::insert(K&&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:922:16, inlined from 'virtual void Yosys::CellmatchPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/techmap/cellmatch.cc:200:21: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {long long unsigned int, int&}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::pool::do_insert(K&&, int&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:808:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::pool::insert(K&&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:922:16, inlined from 'virtual void Yosys::CellmatchPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/techmap/cellmatch.cc:200:21: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {long long unsigned int, int}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::pool::do_insert(K&&, int&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:804:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::pool::insert(K&&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:922:16, inlined from 'virtual void Yosys::CellmatchPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/techmap/cellmatch.cc:233:21: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In member function 'void std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {long long unsigned int, int&}; _Tp = Yosys::hashlib::pool::entry_t; _Alloc = std::allocator::entry_t>]', inlined from 'int Yosys::hashlib::pool::do_insert(K&&, int&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:808:24, inlined from 'std::pair::iterator, bool> Yosys::hashlib::pool::insert(K&&) [with K = long long unsigned int; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:922:16, inlined from 'virtual void Yosys::CellmatchPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/techmap/cellmatch.cc:233:21: /usr/include/c++/13.2.1/bits/vector.tcc:123:28: note: parameter passing for argument of type '__gnu_cxx::__normal_iterator::entry_t*, std::vector::entry_t, std::allocator::entry_t> > >' changed in GCC 7.1 123 | _M_realloc_insert(end(), std::forward<_Args>(__args)...); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [ 99%] Building kernel/python_wrappers.o [100%] Building yosys [100%] Building libyosys.so Build successful. [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 [ 0%] Building kernel/version_9b6afcf3f83.cc [ 0%] Building kernel/version_9b6afcf3f83.o [100%] Building yosys [100%] Building libyosys.so cd tests/simple && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/simple' + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c+ gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o + /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata gcc -Wall /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c-o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c+ + gcc gcc -Wall -Wall -o -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c+ gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + + gcc gcc -Wall -Wall -o -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c+ gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + + gcc gcc -Wall -Wall -o -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c + gcc -Wall -o /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/tools/cmp_tbdata.c Test: case_expr_extend -> ok Test: genblk_order -> ok Test: genblk_dive -> ok Test: genblk_port_shadow -> ok Test: local_loop_var -> ok Test: case_expr_const -> ok Test: nested_genblk_resolve -> ok Test: case_expr_non_const -> ok Test: case_expr_query -> ok Test: const_branch_finish -> ok Test: unnamed_block_decl -> ok Test: matching_end_labels -> ok Test: ifdef_1 -> ok Test: ifdef_2 -> ok Test: named_genblk -> ok Test: macro_arg_surrounding_spaces -> ok Test: memwr_port_connection -> ok Test: loop_var_shadow -> ok Test: param_attr -> ok Test: localparam_attr -> ok Test: genblk_collide -> ok Test: module_scope_case -> ok Test: loop_prefix_case -> ok Test: always01 -> ok Test: arrays02 -> ok Test: omsp_dbg_uart -> ok Test: attrib02_port_decl -> ok Test: attrib01_module -> ok Test: attrib08_mod_inst -> ok Test: hierarchy -> ok Test: forgen01 -> ok Test: arrays01 -> ok Test: graphtest -> ok Test: always02 -> ok Test: lesser_size_cast -> ok Test: aes_kexp128 -> ok Test: mem2reg_bounds_tern -> ok Test: module_scope -> ok Test: attrib06_operator_suffix -> ok Test: func_recurse -> ok Test: carryadd -> ok Test: module_scope_func -> ok Test: fiedler-cooley -> ok Test: const_fold_func -> ok Test: forgen02 -> ok Test: attrib03_parameter -> ok Test: forloops -> ok Test: undef_eqx_nex -> ok Test: specify -> ok Test: attrib09_case -> ok Test: macros -> ok Test: defvalue -> ok Test: retime -> ok Test: attrib04_net_var -> ok Test: implicit_ports -> ok Test: macro_arg_spaces -> ok Test: realexpr -> ok Test: func_block -> ok Test: always03 -> ok Test: signedexpr -> ok Test: fsm -> ok Test: usb_phy_tests -> ok Test: verilog_primitives -> ok Test: loops -> ok Test: arraycells -> ok Test: dff_init -> ok Test: func_width_scope -> ok Test: muxtree -> ok Test: constpower -> ok Test: signed_full_slice -> ok Test: scopes -> ok Test: sign_part_assign -> ok Test: i2c_master_tests -> ok Test: hierdefparam -> ok Test: repwhile -> ok Test: values -> ok Test: arrays03 -> ok Test: subbytes -> ok Test: process -> ok Test: paramods -> ok Test: dff_different_styles -> ok Test: wandwor -> ok Test: const_func_shadow -> ok Test: multiplier -> ok Test: mem_arst -> ok Test: wreduce -> ok Test: task_func -> ok Test: constmuldivmod -> ok Test: vloghammer -> ok Test: mem2reg -> ok Test: dynslice -> ok Test: sincos -> ok Test: generate -> ok Test: asgn_binop -> ok Test: operators -> ok Test: case_large -> ok Test: rotate -> ok Test: memory -> ok Test: partsel -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/simple' cd tests/simple_abc9 && bash run-test.sh "" ls: *.sv: No such file or directory make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/simple_abc9' Test: const_branch_finish -> ok Test: named_genblk -> ok Test: nested_genblk_resolve -> ok Test: genblk_order -> ok Test: loop_var_shadow -> ok Test: genblk_collide -> ok Test: genblk_dive -> ok Test: case_expr_non_const -> ok Test: macro_arg_surrounding_spaces -> ok Test: param_attr -> ok Test: genblk_port_shadow -> ok Test: case_expr_const -> ok Test: omsp_dbg_uart -> ok Test: always01 -> ok Test: module_scope_func -> ok Test: loop_prefix_case -> ok Test: always03 -> ok Test: ifdef_1 -> ok Test: ifdef_2 -> ok Test: attrib01_module -> ok Test: arrays01 -> ok Test: carryadd -> ok Test: attrib08_mod_inst -> ok Test: always02 -> ok Test: forgen01 -> ok Test: localparam_attr -> ok Test: undef_eqx_nex -> ok Test: const_fold_func -> ok Test: attrib02_port_decl -> ok Test: func_recurse -> ok Test: retime -> ok Test: attrib09_case -> ok Test: module_scope_case -> ok Test: forgen02 -> ok Test: graphtest -> ok Test: hierarchy -> ok Test: aes_kexp128 -> ok Test: fsm -> ok Test: func_block -> ok Test: attrib04_net_var -> ok Test: mem2reg_bounds_tern -> ok Test: signedexpr -> ok Test: attrib03_parameter -> ok Test: muxtree -> ok Test: attrib06_operator_suffix -> ok Test: arraycells -> ok Test: sign_part_assign -> ok Test: usb_phy_tests -> ok Test: func_width_scope -> ok Test: macros -> ok Test: verilog_primitives -> ok Test: forloops -> ok Test: subbytes -> ok Test: fiedler-cooley -> ok Test: case_expr_query -> ok Test: case_expr_extend -> ok Test: dff_init -> ok Test: arrays02 -> ok Test: local_loop_var -> ok Test: matching_end_labels -> ok Test: unnamed_block_decl -> ok Test: scopes -> ok Test: repwhile -> ok Test: memwr_port_connection -> ok Test: lesser_size_cast -> ok Test: i2c_master_tests -> ok Test: signed_full_slice -> ok Test: process -> ok Test: realexpr -> ok Test: module_scope -> ok Test: mem_arst -> ok Test: loops -> ok Test: implicit_ports -> ok Test: values -> ok Test: hierdefparam -> ok Test: constpower -> ok Test: defvalue -> ok Test: dff_different_styles -> ok Test: paramods -> ok Test: wandwor -> ok Test: const_func_shadow -> ok Test: mem2reg -> ok Test: vloghammer -> ok Test: arrays03 -> ok Test: multiplier -> ok Test: task_func -> ok Test: macro_arg_spaces -> ok Test: rotate -> ok Test: asgn_binop -> ok Test: constmuldivmod -> ok Test: wreduce -> ok Test: generate -> ok Test: sincos -> ok Test: abc9 -> ok Test: memory -> ok Test: operators -> ok Test: dynslice -> ok Test: case_large -> ok Test: partsel -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/simple_abc9' cd tests/hana && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/hana' Test: test_simulation_buffer -> ok Test: test_simulation_vlib -> ok Test: test_simulation_seq -> ok Test: test_simulation_nor -> ok Test: test_simulation_xnor -> ok Test: test_simulation_xor -> ok Test: test_parse2synthtrans -> ok Test: test_simulation_nand -> ok Test: test_simulation_or -> ok Test: test_simulation_and -> ok Test: test_simulation_inc -> ok Test: test_parser -> ok Test: test_simulation_sop -> ok Test: test_simulation_decoder -> ok Test: test_simulation_techmap -> ok Test: test_simulation_always -> ok Test: test_simulation_mux -> ok Test: test_simulation_shifter -> ok Test: test_simulation_techmap_tech -> ok Test: test_intermout -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/hana' cd tests/asicworld && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/asicworld' Test: code_verilog_tutorial_always_example -> ok Test: code_verilog_tutorial_if_else -> ok Test: code_verilog_tutorial_parallel_if -> ok Test: code_verilog_tutorial_task_global -> ok Test: code_verilog_tutorial_v2k_reg -> ok Test: code_verilog_tutorial_n_out_primitive -> ok Test: code_verilog_tutorial_simple_function -> ok Test: code_verilog_tutorial_simple_if -> ok Test: code_verilog_tutorial_counter -> ok Test: code_verilog_tutorial_first_counter -> ok Test: code_verilog_tutorial_multiply -> ok Test: code_hdl_models_dff_async_reset -> ok Test: code_tidbits_nonblocking -> ok Test: code_verilog_tutorial_which_clock -> ok Test: code_hdl_models_clk_div -> ok Test: code_tidbits_reg_seq_example -> ok Test: code_tidbits_blocking -> ok Test: code_verilog_tutorial_d_ff -> ok Test: code_hdl_models_one_hot_cnt -> ok Test: code_hdl_models_tff_async_reset -> ok Test: code_tidbits_asyn_reset -> ok Test: code_hdl_models_dff_sync_reset -> ok Test: code_tidbits_reg_combo_example -> ok Test: code_hdl_models_tff_sync_reset -> ok Test: code_verilog_tutorial_flip_flop -> ok Test: code_hdl_models_parity_using_assign -> ok Test: code_hdl_models_parity_using_bitwise -> ok Test: code_tidbits_syn_reset -> ok Test: code_hdl_models_lfsr -> ok Test: code_verilog_tutorial_bus_con -> ok Test: code_hdl_models_up_counter -> ok Test: code_verilog_tutorial_parity -> ok Test: code_hdl_models_GrayCounter -> ok Test: code_hdl_models_encoder_4to2_gates -> ok Test: code_hdl_models_rom_using_case -> ok Test: code_hdl_models_gray_counter -> ok Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_parity_using_function -> ok Test: code_tidbits_wire_example -> ok Test: code_verilog_tutorial_escape_id -> ok Test: code_hdl_models_d_latch_gates -> ok Test: code_verilog_tutorial_comment -> ok Test: code_hdl_models_decoder_2to4_gates -> ok Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_mux_using_case -> ok Test: code_verilog_tutorial_good_code -> ok Test: code_verilog_tutorial_decoder_always -> ok Test: code_hdl_models_arbiter -> ok Test: code_hdl_models_mux_using_if -> ok Test: code_hdl_models_decoder_using_case -> ok Test: code_verilog_tutorial_decoder -> ok Test: code_verilog_tutorial_tri_buf -> ok Test: code_hdl_models_mux_2to1_gates -> ok Test: code_hdl_models_full_adder_gates -> ok Test: code_hdl_models_decoder_using_assign -> ok Test: code_tidbits_fsm_using_always -> ok Test: code_hdl_models_full_subtracter_gates -> ok Test: code_verilog_tutorial_addbit -> ok Test: code_hdl_models_mux_using_assign -> ok Test: code_tidbits_fsm_using_function -> ok Test: code_verilog_tutorial_mux_21 -> ok Test: code_hdl_models_lfsr_updown -> ok Test: code_verilog_tutorial_explicit -> ok Test: code_hdl_models_encoder_using_case -> ok Test: code_hdl_models_encoder_using_if -> ok Test: code_hdl_models_clk_div_45 -> ok Test: code_hdl_models_up_counter_load -> ok Test: code_hdl_models_serial_crc -> ok Test: code_hdl_models_parallel_crc -> ok Test: code_hdl_models_pri_encoder_using_assign -> ok Test: code_tidbits_fsm_using_single_always -> ok Test: code_verilog_tutorial_fsm_full -> ok Test: code_hdl_models_up_down_counter -> ok Test: code_specman_switch_fabric -> ok Test: code_hdl_models_uart -> ok Test: code_hdl_models_cam -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/asicworld' # +cd tests/realmath && bash run-test.sh "" cd tests/share && bash run-test.sh "" generating tests.. running tests.. [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] cd tests/opt_share && bash run-test.sh "" generating tests.. running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/opt_share' [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][44][45][43][46][48][49][47][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/opt_share' cd tests/fsm && bash run-test.sh "" generating tests.. PRNG seed: 1266699764 running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/fsm' [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KWarning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KKKKWarning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KKKKKKKKWarning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKTT make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/fsm' cd tests/techmap && bash run-test.sh make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/techmap' Warning: wire '\Q' is assigned in a block at < ok Test: firrtl_938 -> ok Test: no_implicit_en -> ok Test: simple_sram_byte_en -> ok Test: shared_ports -> ok Test: wide_thru_priority -> ok Test: wide_read_async -> ok Test: wide_all -> ok Test: wide_read_sync -> ok Test: trans_sdp -> ok Test: trans_addr_enable -> ok Test: read_two_mux -> ok Test: issue00710 -> ok Test: wide_read_mixed -> ok Test: wide_write -> ok Test: wide_read_trans -> ok Test: trans_sp -> ok Test: read_arst -> ok Test: amber23_sram_byte_en -> ok Test: issue00335 -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/memories' Testing expectations for amber23_sram_byte_en.v .. ok. Testing expectations for implicit_en.v .. ok. Testing expectations for issue00335.v .. ok. Testing expectations for issue00710.v .. ok. Testing expectations for no_implicit_en.v .. ok. Testing expectations for read_arst.v .. ok. Testing expectations for read_two_mux.v .. ok. Testing expectations for shared_ports.v .. ok. Testing expectations for simple_sram_byte_en.v .. ok. Testing expectations for trans_addr_enable.v .. ok. Testing expectations for trans_sdp.v .. ok. Testing expectations for trans_sp.v .. ok. Testing expectations for wide_all.v .. ok. Testing expectations for wide_read_async.v .. ok. Testing expectations for wide_read_mixed.v .. ok. Testing expectations for wide_read_sync.v .. ok. Testing expectations for wide_read_trans.v .. ok. Testing expectations for wide_thru_priority.v .. ok. Testing expectations for wide_write.v .. ok. cd tests/memlib && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/memlib' Test: t_ram_1b1B -> ok Test: t_mixed_18_9 -> ok Test: t_clock_a4_wANYrNEGsFalse -> ok Test: t_sp_new_new -> ok Test: t_ram_18b2B -> ok Test: t_init_18b2B_val_no_undef -> ok Test: t_init_9b1B_zeros_zero -> ok Test: t_clock_a4_wANYrANYsFalse -> ok Test: t_init_4b1B_x_zero -> ok Test: t_sync_trans_old_old -> ok Test: t_mixed_36_9 -> ok Test: t_sp_old_none -> ok Test: t_init_4b1B_x_no_undef -> ok Test: t_clock_a4_wPOSrNEGsFalse -> ok Test: t_clock_a4_wNEGrNEGsTrue -> ok Test: t_clock_a4_wNEGrNEGsFalse -> ok Test: t_clock_a4_wPOSrPOSsFalse -> ok Test: t_sp_nc_nc -> ok Test: t_clock_a4_wPOSrPOSsTrue -> ok Test: t_sync_trans_old_new -> ok Test: t_clock_a4_wPOSrNEGsTrue -> ok Test: t_ram_9b1B -> ok Test: t_sp_nc_new_only -> ok Test: t_clock_a4_wNEGrPOSsFalse -> ok Test: t_sp_nc_new -> ok Test: t_sync_2clk -> ok Test: t_sp_new_nc -> ok Test: t_sp_nc_none -> ok Test: t_init_9b1B_val_no_undef -> ok Test: t_sync_small -> ok Test: t_ram_2b1B -> ok Test: t_sp_nc_old -> ok Test: t_clock_a4_wNEGrPOSsTrue -> ok Test: t_init_9b1B_val_any -> ok Test: t_sp_old_old -> ok Test: t_clock_a4_wANYrPOSsFalse -> ok Test: t_init_9b1B_val_zero -> ok Test: t_sync_trans_new_old -> ok Test: t_sp_new_none -> ok Test: t_init_lut_x_none -> ok Test: t_sync_small_block -> ok Test: t_sync_big -> ok Test: t_init_lut_x_any -> ok Test: t_async_small -> ok Test: t_sp_new_old -> ok Test: t_sync_trans_new_none -> ok Test: t_unmixed -> ok Test: t_sp_old_nc -> ok Test: t_ram_4b1B -> ok Test: t_sync_small_block_attr -> ok Test: t_init_13b2B_val_any -> ok Test: t_init_4b1B_x_any -> ok Test: t_init_lut_val_zero -> ok Test: t_clock_a4_wPOSrANYsFalse -> ok Test: t_mixed_4_2 -> ok Test: t_init_lut_val_any -> ok Test: t_sync_big_sdp -> ok Test: t_clock_a4_wNEGrANYsFalse -> ok Test: t_tdp -> ok Test: t_clock_a4_wANYrANYsTrue -> ok Test: t_init_18b2B_val_any -> ok Test: t_init_lut_val2_no_undef -> ok Test: t_init_lut_x_zero -> ok Test: t_sync_shared -> ok Test: t_init_4b1B_x_none -> ok Test: t_sync_trans_new_new -> ok Test: t_sp_old_new -> ok Test: t_init_lut_x_no_undef -> ok Test: t_init_9b1B_zeros_any -> ok Test: t_sync_trans_old_none -> ok Test: t_init_lut_zeros_any -> ok Test: t_init_lut_val_no_undef -> ok Test: t_init_lut_zeros_zero -> ok Test: t_async_small_block -> ok Test: t_sync_2clk_shared -> ok Test: t_init_lut_val2_any -> ok Test: t_mixed_9_18 -> ok Test: t_sp_new_new_only -> ok Test: t_sp_new_nc_be -> ok Test: t_sp_new_new_be -> ok Test: t_sp_nc_new_only_be -> ok Test: t_sp_nc_new_be -> ok Test: t_sp_new_new_only_be -> ok Test: t_sp_old_auto_be -> ok Test: t_sp_new_auto_be -> ok Test: t_sp_nc_auto -> ok Test: t_sp_old_new_be -> ok Test: t_sp_old_old_be -> ok Test: t_sp_new_old_be -> ok Test: t_sp_old_new_only_be -> ok Test: t_sp_arst_0_any_re -> ok Test: t_sp_nc_auto_be -> ok Test: t_sp_new_auto -> ok Test: t_sp_arst_0_x -> ok Test: t_sp_old_new_only -> ok Test: t_sp_arst_x_x -> ok Test: t_sp_old_auto -> ok Test: t_sp_arst_v_x_re -> ok Test: t_sp_arst_0_x_re -> ok Test: t_sp_old_nc_be -> ok Test: t_sp_init_x_x_ce -> ok Test: t_sp_nc_old_be -> ok Test: t_sp_arst_n_0 -> ok Test: t_sp_arst_v_init -> ok Test: t_sp_init_v_any_re -> ok Test: t_sp_arst_0_init -> ok Test: t_sp_nc_nc_be -> ok Test: t_sp_arst_v_init_re -> ok Test: t_sp_arst_e_0 -> ok Test: t_sp_arst_n_init -> ok Test: t_sp_init_0_any_re -> ok Test: t_sp_init_0_0_re -> ok Test: t_sp_init_v_any -> ok Test: t_sp_arst_n_any -> ok Test: t_sp_init_x_x_re -> ok Test: t_sp_arst_n_0_re -> ok Test: t_sp_arst_v_any_re -> ok Test: t_sp_init_v_x -> ok Test: t_sp_arst_0_0_re -> ok Test: t_sp_init_x_x -> ok Test: t_sp_init_0_any -> ok Test: t_sp_arst_v_0 -> ok Test: t_sp_arst_x_x_re -> ok Test: t_sp_init_0_x_re -> ok Test: t_sp_init_v_0_re -> ok Test: t_sp_arst_v_any -> ok Test: t_sp_arst_v_x -> ok Test: t_sp_arst_e_init -> ok Test: t_sp_arst_e_0_re -> ok Test: t_sp_arst_e_x_re -> ok Test: t_sp_arst_e_init_re -> ok Test: t_sp_init_0_x -> ok Test: t_sp_init_0_0 -> ok Test: t_sp_arst_n_x_re -> ok Test: t_sp_arst_n_x -> ok Test: t_sp_arst_e_any_re -> ok Test: t_sp_init_v_x_re -> ok Test: t_sp_arst_0_any -> ok Test: t_sp_srst_x_x_re -> ok Test: t_sp_arst_n_any_re -> ok Test: t_sp_arst_e_x -> ok Test: t_sp_init_v_0 -> ok Test: t_sp_arst_0_0 -> ok Test: t_sp_arst_e_any -> ok Test: t_sp_arst_v_0_re -> ok Test: t_sp_arst_0_init_re -> ok Test: t_sp_srst_0_0 -> ok Test: t_sp_arst_n_init_re -> ok Test: t_sp_srst_0_x_re -> ok Test: t_sp_srst_0_0_re -> ok Test: t_sp_srst_x_x -> ok Test: t_sp_srst_0_x -> ok Test: t_sp_srst_0_any -> ok Test: t_sp_srst_0_init -> ok Test: t_sp_srst_v_0_re -> ok Test: t_sp_srst_e_0_re -> ok Test: t_sp_srst_n_any_re -> ok Test: t_sp_srst_e_0 -> ok Test: t_sp_srst_v_any_ce -> ok Test: t_sp_srst_0_any_re -> ok Test: t_sp_srst_v_init -> ok Test: t_sp_srst_v_any_re_gated -> ok Test: t_sp_srst_v_any_re -> ok Test: t_sp_srst_e_x -> ok Test: t_sp_srst_0_init_re -> ok Test: t_sp_srst_e_init_re -> ok Test: t_sp_srst_n_any -> ok Test: t_sp_srst_n_x -> ok Test: t_sp_srst_v_init_re -> ok Test: t_sp_srst_n_0_re -> ok Test: t_sp_srst_v_x -> ok Test: t_sp_srst_n_init -> ok Test: t_sp_srst_e_x_re -> ok Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_v_any_ce_gated -> ok Test: t_wren_a4d8_W8_B8 -> ok Test: t_sp_srst_v_x_re -> ok Test: t_sp_srst_gv_any_re -> ok Test: t_wren_a4d8_NO_BYTE -> ok Test: t_sp_srst_n_x_re -> ok Test: t_wren_a5d4_NO_BYTE -> ok Test: t_sp_srst_e_any -> ok Test: t_sp_srst_v_0 -> ok Test: t_sp_srst_gv_init_re -> ok Test: t_sp_srst_v_any -> ok Test: t_sp_srst_e_any_re -> ok Test: t_sp_srst_e_init -> ok Test: t_wren_a4d8_W8_B4 -> ok Test: t_sp_srst_gv_any_ce_gated -> ok Test: t_wren_a6d4_NO_BYTE -> ok Test: t_sp_srst_n_0 -> ok Test: t_sp_srst_gv_any -> ok Test: t_wren_a4d4_NO_BYTE -> ok Test: t_wren_a3d8_NO_BYTE -> ok Test: t_sp_srst_gv_x -> ok Test: t_sp_srst_gv_x_re -> ok Test: t_wren_a5d4w2_W16_B4_separate -> ok Test: t_wren_a4d4w4_W16_B4_separate -> ok Test: t_wren_a4d8_W8_B4_separate -> ok Test: t_sp_srst_gv_any_re_gated -> ok Test: t_sp_srst_gv_any_ce -> ok Test: t_sp_srst_gv_0 -> ok Test: t_wren_a4d4w4_W16_B4 -> ok Test: t_sp_srst_gv_0_re -> ok Test: t_wren_a5d8w1_W16_B4_separate -> ok Test: t_wren_a4d8_W4_B4_separate -> ok Test: t_wren_a4d8w2_W16_B4 -> ok Test: t_wren_a4d8_W8_B8_separate -> ok Test: t_wren_a4d4_W4_B4 -> ok Test: t_wren_a4d2w8_W16_B4 -> ok Test: t_wren_a4d8w2_W16_B4_separate -> ok Test: t_wren_a5d8w1_W16_B4 -> ok Test: t_wren_a5d4w2_W16_B4 -> ok Test: t_sp_srst_gv_init -> ok Test: t_wren_a4d4w1_W8_B8 -> ok Test: t_wren_a5d4w4_W16_B4_separate -> ok Test: t_wren_a4d16w1_W16_B4_separate -> ok Test: t_wren_a5d8w2_W16_B4 -> ok Test: t_wren_a4d4w2_W8_B8 -> ok Test: t_wren_a4d16w1_W16_B4 -> ok Test: t_wren_a5d4w4_W16_B4 -> ok Test: t_wren_a4d4w1_W8_B8_separate -> ok Test: t_wren_a4d2w8_W16_B4_separate -> ok Test: t_wren_a4d8w2_W8_B8_separate -> ok Test: t_wren_a3d8w2_W8_B8 -> ok Test: t_wren_a4d8w2_W8_B8 -> ok Test: t_wren_a4d4w2_W8_B4_separate -> ok Test: t_wren_a5d8w2_W16_B4_separate -> ok Test: t_wren_a4d4w2_W8_B8_separate -> ok Test: t_wren_a4d4w2_W8_B4 -> ok Test: t_wren_a3d8w2_W8_B8_separate -> ok Test: t_geom_a4d64_wren -> ok Test: t_wren_a4d4w4_W8_B4 -> ok Test: t_geom_a5d32_wren -> ok Test: t_wren_a4d4w4_W4_B4_separate -> ok Test: t_geom_a6d16_wren -> ok Test: t_geom_a3d18_9b1B -> ok Test: t_geom_a4d4_9b1B -> ok Test: t_wren_a4d2w4_W8_B4 -> ok Test: t_wren_a4d4w4_W8_B4_separate -> ok Test: t_geom_a5d64_wren -> ok Test: t_wren_a4d4w5_W4_B4_separate -> ok Test: t_wren_a4d2w4_W8_B4_separate -> ok Test: t_wren_a4d4w4_W4_B4 -> ok Test: t_geom_a4d18_9b1B -> ok Test: t_geom_a6d64_wren -> ok Test: t_geom_a6d4_9b1B -> ok Test: t_geom_a7d8_wren -> ok Test: t_geom_a6d30_wren -> ok Test: t_geom_a5d32_9b1B -> ok Test: t_geom_a7d6_wren -> ok Test: t_wren_a4d4w5_W4_B4 -> ok Test: t_geom_a7d4_wren -> ok Test: t_wide_sdp_a6r2w0b0x0 -> ok Test: t_geom_a7d17_wren -> ok Test: t_wide_sdp_a8r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w1b0x0 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok Test: t_geom_a7d11_9b1B -> ok Test: t_wide_sdp_a6r0w3b2x0 -> ok Test: t_wide_sdp_a7r0w0b0x0 -> ok Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w2b0x0 -> ok Test: t_wide_sdp_a6r4w0b0x0 -> ok Test: t_wide_sdp_a7r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w2b2x0 -> ok Test: t_wide_sdp_a6r1w0b0x0 -> ok Test: t_wide_sdp_a7r0w1b0x0 -> ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sp_mix_a8r1w1b1 -> ok Test: t_wide_sdp_a7r2w0b0x0 -> ok Test: t_geom_a8d6_wren -> ok Test: t_geom_a8d4_wren -> ok Test: t_wide_sdp_a6r0w1b1x0 -> ok Test: t_wide_sdp_a7r0w2b2x0 -> ok Test: t_geom_a7d18_9b1B -> ok Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_geom_a9d5_wren -> ok Test: t_geom_a9d4_wren -> ok Test: t_geom_a9d8_wren -> ok Test: t_wide_sp_mix_a6r1w0b0 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_geom_a11d1_9b1B -> ok Test: t_wide_sp_mix_a7r1w1b1 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_geom_a9d6_wren -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r0w2b2 -> ok Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r5w0b0 -> ok Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sp_mix_a6r4w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok Test: t_wide_sp_mix_a7r0w0b0 -> ok Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok Test: t_wide_sp_mix_a7r4w0b0 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok Test: t_wide_sp_mix_a7r0w2b2 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w0b0 -> ok Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_mix_a7r0w4b2 -> ok Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b1 -> ok Test: t_wide_sp_mix_a7r0w3b2 -> ok Test: t_wide_sp_tied_a6r0w1b0 -> ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_mix_a6r0w5b2 -> ok Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_tied_a7r0w1b0 -> ok Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok Test: t_wide_sp_tied_a7r0w2b2 -> ok Test: t_wide_sp_tied_a6r0w2b2 -> ok Test: t_wide_read_a6r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w1b1 -> ok Test: t_wide_read_a7r1w1b1 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok Test: t_wide_read_a6r2w0b0 -> ok Test: t_wide_sp_tied_a7r0w3b2 -> ok Test: t_wide_write_a6r1w1b1 -> ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok Test: t_wide_read_a6r0w0b0 -> ok Test: t_wide_sp_tied_a7r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w5b2 -> ok Test: t_wide_sp_tied_a7r3w0b0 -> ok Test: t_wide_write_a6r1w0b0 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok Test: t_wide_read_a6r0w2b0 -> ok Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_write_a7r1w1b1 -> ok Test: t_wide_write_a6r0w2b0 -> ok Test: t_wide_read_a6r0w2b2 -> ok Test: t_wide_sp_tied_a7r4w0b0 -> ok Test: t_wide_write_a6r2w0b0 -> ok Test: t_wide_sp_tied_a6r4w0b0 -> ok Test: t_wide_write_a6r0w1b1 -> ok Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_write_a6r0w0b0 -> ok Test: t_wide_read_a6r4w0b0 -> ok Test: t_wide_read_a6r3w0b0 -> ok Test: t_wide_write_a6r0w2b2 -> ok Test: t_wide_read_a6r0w1b0 -> ok Test: t_wide_read_a6r5w0b0 -> ok Test: t_wide_sp_tied_a6r5w0b0 -> ok Test: t_wide_write_a6r0w1b0 -> ok Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_write_a6r0w3b2 -> ok Test: t_wide_write_a6r3w0b0 -> ok Test: t_wide_sp_tied_a7r0w5b2 -> ok Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_read_a7r0w0b0 -> ok Test: t_wide_read_a7r2w0b0 -> ok Test: t_wide_read_a6r0w4b2 -> ok Test: t_wide_write_a6r4w0b0 -> ok Test: t_wide_read_a7r1w0b0 -> ok Test: t_wide_sp_tied_a7r5w0b0 -> ok Test: t_wide_quad_a4w2r1 -> ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_quad_port_a4d2 -> ok Test: t_wide_read_a7r0w1b0 -> ok Test: t_quad_port_a5d2 -> ok Test: t_wide_read_a7r0w1b1 -> ok Test: t_wide_write_a7r0w0b0 -> ok Test: t_wide_quad_a4w2r5 -> ok Test: t_quad_port_a4d4 -> ok Test: t_wide_read_a7r0w2b0 -> ok Test: t_wide_oct_a4w2r3 -> ok Test: t_quad_port_a2d2 -> ok Test: t_wide_read_a7r3w0b0 -> ok Test: t_quad_port_a4d8 -> ok Test: t_wide_write_a7r0w1b1 -> ok Test: t_wide_write_a6r0w5b2 -> ok Test: t_wide_write_a7r1w0b0 -> ok Test: t_wide_quad_a4w2r3 -> ok Test: t_wide_write_a7r0w2b2 -> ok Test: t_quad_port_a6d2 -> ok Test: t_wide_quad_a4w2r7 -> ok Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_write_a7r0w2b0 -> ok Test: t_wide_quad_a4w2r6 -> ok Test: t_wide_quad_a4w4r1 -> ok Test: t_wide_oct_a4w2r2 -> ok Test: t_wide_oct_a4w2r1 -> ok Test: t_wide_write_a7r0w1b0 -> ok Test: t_wide_quad_a4w2r2 -> ok Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w3b2 -> ok Test: t_wide_read_a7r4w0b0 -> ok Test: t_wide_quad_a4w2r4 -> ok Test: t_wide_oct_a5w2r1 -> ok Test: t_wide_quad_a4w4r4 -> ok Test: t_wide_oct_a4w2r7 -> ok Test: t_wide_quad_a4w2r8 -> ok Test: t_wide_write_a7r0w4b2 -> ok Test: t_wide_read_a6r0w5b2 -> ok Test: t_wide_read_a7r5w0b0 -> ok Test: t_wide_oct_a4w2r4 -> ok Test: t_wide_oct_a4w2r5 -> ok Test: t_wide_quad_a5w2r1 -> ok Test: t_wide_oct_a4w4r4 -> ok Test: t_wide_oct_a4w2r9 -> ok Test: t_wide_oct_a4w4r1 -> ok Test: t_wide_oct_a4w2r6 -> ok Test: t_wide_quad_a4w2r9 -> ok Test: t_wide_write_a7r3w0b0 -> ok Test: t_wide_oct_a4w2r8 -> ok Test: t_wide_read_a7r0w4b2 -> ok Test: t_wide_oct_a4w4r9 -> ok Test: t_wide_oct_a5w2r4 -> ok Test: t_wide_quad_a4w4r9 -> ok Test: t_wide_oct_a4w4r6 -> ok Test: t_wide_quad_a5w2r4 -> ok Test: t_wide_write_a7r4w0b0 -> ok Test: t_wide_quad_a4w4r6 -> ok Test: t_wide_write_a7r0w5b2 -> ok Test: t_gclken -> ok Test: t_no_reset -> ok Test: t_grden -> ok Test: t_rom_case -> ok Test: t_wide_oct_a5w2r9 -> ok Test: t_rom_case_block -> ok Test: t_exclwr -> ok Test: t_wide_read_a7r0w5b2 -> ok Test: t_grden_ce -> ok Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_quad_a5w2r9 -> ok Test: t_excl_rst -> ok Test: t_transwr -> ok Test: t_ungated -> ok Test: t_trans_byte -> ok Test: t_trans_rst -> ok Test: t_gclken_ce -> ok Test: t_wr_byte -> ok Test: t_wr_rst_byte -> ok Test: t_rdenrst_wr_byte -> ok Test: t_rst_wr_byte -> ok Test: t_wide_write_a7r5w0b0 -> ok Test: t_async_big -> ok Test: t_sync_big_lut -> ok Test: t_async_big_block -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/memlib' cd tests/bram && bash run-test.sh "" generating tests.. PRNG seed: 492100 running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/bram' Passed memory_bram test 02_00. Passed memory_bram test 01_00. Passed memory_bram test 01_04. Passed memory_bram test 02_04. Passed memory_bram test 00_04. Passed memory_bram test 01_02. Passed memory_bram test 03_04. Passed memory_bram test 03_00. Passed memory_bram test 02_01. Passed memory_bram test 00_02. Passed memory_bram test 01_03. Passed memory_bram test 03_02. Passed memory_bram test 02_03. Passed memory_bram test 00_03. Passed memory_bram test 04_00. Passed memory_bram test 04_02. Passed memory_bram test 00_01. Passed memory_bram test 04_03. Passed memory_bram test 04_01. Passed memory_bram test 03_01. make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/bram' cd tests/various && bash run-test.sh make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/various' Warning: Yosys has only limited support for tri-state logic at the moment. (< Y[0] wire \ripple [0] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < Y[0] cell $memrd$\mem$< DATA[0] wire \data [0] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < Y[0] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[0] --> Q[0] wire \dword [0] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[0] --> Y[0] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[1] --> Y[1] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[1] --> Q[1] wire \dword [1] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[1] --> Y[1] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[2] --> Y[2] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[2] --> Q[2] wire \dword [2] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[2] --> Y[2] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[3] --> Y[3] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[3] --> Q[3] wire \dword [3] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[3] --> Y[3] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[4] --> Y[4] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[4] --> Q[4] wire \dword [4] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[4] --> Y[4] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[5] --> Y[5] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[5] --> Q[5] wire \dword [5] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[5] --> Y[5] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[6] --> Y[6] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[6] --> Q[6] wire \dword [6] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[6] --> Y[6] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[7] --> Y[7] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[7] --> Q[7] wire \dword [7] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[7] --> Y[7] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[8] --> Y[8] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[8] --> Q[8] wire \dword [8] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[8] --> Y[8] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[9] --> Y[9] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[9] --> Q[9] wire \dword [9] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[9] --> Y[9] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[10] --> Y[10] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[10] --> Q[10] wire \dword [10] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[10] --> Y[10] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[11] --> Y[11] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[11] --> Q[11] wire \dword [11] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[11] --> Y[11] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[12] --> Y[12] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[12] --> Q[12] wire \dword [12] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[12] --> Y[12] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[13] --> Y[13] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[13] --> Q[13] wire \dword [13] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[13] --> Y[13] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[14] --> Y[14] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[14] --> Q[14] wire \dword [14] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[14] --> Y[14] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[15] --> Y[15] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[15] --> Q[15] wire \dword [15] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[15] --> Y[15] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[16] --> Y[16] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[16] --> Q[16] wire \dword [16] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[16] --> Y[16] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[17] --> Y[17] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[17] --> Q[17] wire \dword [17] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[17] --> Y[17] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[18] --> Y[18] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[18] --> Q[18] wire \dword [18] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[18] --> Y[18] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[19] --> Y[19] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[19] --> Q[19] wire \dword [19] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[19] --> Y[19] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[20] --> Y[20] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[20] --> Q[20] wire \dword [20] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[20] --> Y[20] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[21] --> Y[21] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[21] --> Q[21] wire \dword [21] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[21] --> Y[21] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[22] --> Y[22] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[22] --> Q[22] wire \dword [22] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[22] --> Y[22] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[23] --> Y[23] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[23] --> Q[23] wire \dword [23] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[23] --> Y[23] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[24] --> Y[24] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[24] --> Q[24] wire \dword [24] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[24] --> Y[24] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[25] --> Y[25] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[25] --> Q[25] wire \dword [25] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[25] --> Y[25] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[26] --> Y[26] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[26] --> Q[26] wire \dword [26] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[26] --> Y[26] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[27] --> Y[27] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[27] --> Q[27] wire \dword [27] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[27] --> Y[27] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[28] --> Y[28] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[28] --> Q[28] wire \dword [28] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[28] --> Y[28] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[29] --> Y[29] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[29] --> Q[29] wire \dword [29] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[29] --> Y[29] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[30] --> Y[30] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[30] --> Q[30] wire \dword [30] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[30] --> Y[30] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[31] --> Y[31] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[31] --> Q[31] wire \dword [31] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[31] --> Y[31] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[32] --> Y[32] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[32] --> Q[32] wire \dword [32] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[32] --> Y[32] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[33] --> Y[33] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[33] --> Q[33] wire \dword [33] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[33] --> Y[33] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[34] --> Y[34] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[34] --> Q[34] wire \dword [34] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[34] --> Y[34] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[35] --> Y[35] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[35] --> Q[35] wire \dword [35] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[35] --> Y[35] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[36] --> Y[36] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[36] --> Q[36] wire \dword [36] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[36] --> Y[36] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[37] --> Y[37] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[37] --> Q[37] wire \dword [37] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[37] --> Y[37] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[38] --> Y[38] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[38] --> Q[38] wire \dword [38] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[38] --> Y[38] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[39] --> Y[39] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[39] --> Q[39] wire \dword [39] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[39] --> Y[39] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[40] --> Y[40] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[40] --> Q[40] wire \dword [40] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[40] --> Y[40] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[41] --> Y[41] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[41] --> Q[41] wire \dword [41] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[41] --> Y[41] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[42] --> Y[42] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[42] --> Q[42] wire \dword [42] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[42] --> Y[42] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[43] --> Y[43] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[43] --> Q[43] wire \dword [43] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[43] --> Y[43] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[44] --> Y[44] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[44] --> Q[44] wire \dword [44] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[44] --> Y[44] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[45] --> Y[45] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[45] --> Q[45] wire \dword [45] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[45] --> Y[45] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[46] --> Y[46] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[46] --> Q[46] wire \dword [46] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[46] --> Y[46] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[47] --> Y[47] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[47] --> Q[47] wire \dword [47] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[47] --> Y[47] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[48] --> Y[48] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[48] --> Q[48] wire \dword [48] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[48] --> Y[48] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[49] --> Y[49] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[49] --> Q[49] wire \dword [49] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[49] --> Y[49] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[50] --> Y[50] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[50] --> Q[50] wire \dword [50] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[50] --> Y[50] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[51] --> Y[51] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[51] --> Q[51] wire \dword [51] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[51] --> Y[51] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[52] --> Y[52] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[52] --> Q[52] wire \dword [52] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[52] --> Y[52] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[53] --> Y[53] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[53] --> Q[53] wire \dword [53] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[53] --> Y[53] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[54] --> Y[54] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[54] --> Q[54] wire \dword [54] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[54] --> Y[54] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[55] --> Y[55] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[55] --> Q[55] wire \dword [55] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[55] --> Y[55] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[56] --> Y[56] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[56] --> Q[56] wire \dword [56] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[56] --> Y[56] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[57] --> Y[57] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[57] --> Q[57] wire \dword [57] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[57] --> Y[57] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[58] --> Y[58] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[58] --> Q[58] wire \dword [58] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[58] --> Y[58] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[59] --> Y[59] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[59] --> Q[59] wire \dword [59] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[59] --> Y[59] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[60] --> Y[60] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[60] --> Q[60] wire \dword [60] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[60] --> Y[60] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[61] --> Y[61] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[61] --> Q[61] wire \dword [61] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[61] --> Y[61] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[62] --> Y[62] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[62] --> Q[62] wire \dword [62] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[62] --> Y[62] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[63] --> Y[63] cell $auto$proc_dlatch.cc:433:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[63] --> Q[63] wire \dword [63] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[63] --> Y[63] Passed dynamic_part_select.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/various' cd tests/select && bash run-test.sh Running blackboxes.ys.. Running no_warn_assert.ys.. Running no_warn_prefixed_arg_memb.ys.. Running no_warn_prefixed_empty_select_arg.ys.. Running unset.ys.. ERROR: Selection '\foo' does not exist! Expected error pattern 'Selection '\\foo' does not exist!' found !!! Running unset2.ys.. ERROR: Selection @foo is not defined! Expected error pattern 'Selection @foo is not defined!' found !!! Running warn_empty_select_arg.ys.. Warning: Selection "foo" did not match any module. Warning: Selection "bar" did not match any object. cd tests/sat && bash run-test.sh make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/sat' Warning: Complex async reset for dff `\q [12]'. Warning: Complex async reset for dff `\q [8]'. Passed bug2595.ys Warning: Wire top.\cnt [7] is used but has no driver. Warning: Wire top.\cnt [6] is used but has no driver. Warning: Wire top.\cnt [5] is used but has no driver. Warning: Wire top.\cnt [4] is used but has no driver. Warning: Wire top.\cnt [3] is used but has no driver. Warning: Wire top.\cnt [2] is used but has no driver. Warning: Wire top.\cnt [1] is used but has no driver. Warning: Wire top.\cnt [0] is used but has no driver. Passed dff.ys Passed initval.ys Passed asserts.ys Passed sizebits.ys Passed splice.ys Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000' ERROR: Signal difference Expected error pattern 'Signal difference' found !!! Passed sim_counter.ys Passed expose_dff.ys Passed asserts_seq.ys Passed counters.ys Passed counters-repeat.ys Passed grom.ys Passed share.ys Passed clk2fflogic.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/sat' cd tests/sim && bash run-test.sh Generate FST for sim models Test tb_adff FST info: dumpfile tb_adff.fst opened for output. tb/tb_adff.v:38: $finish called at 110 (1ns) Test tb_adffe FST info: dumpfile tb_adffe.fst opened for output. tb/tb_adffe.v:56: $finish called at 190 (1ns) Test tb_adlatch FST info: dumpfile tb_adlatch.fst opened for output. tb/tb_adlatch.v:68: $finish called at 250 (1ns) Test tb_aldff FST info: dumpfile tb_aldff.fst opened for output. tb/tb_aldff.v:71: $finish called at 270 (1ns) Test tb_aldffe FST info: dumpfile tb_aldffe.fst opened for output. tb/tb_aldffe.v:73: $finish called at 270 (1ns) Test tb_dff FST info: dumpfile tb_dff.fst opened for output. tb/tb_dff.v:45: $finish called at 150 (1ns) Test tb_dffe FST info: dumpfile tb_dffe.fst opened for output. tb/tb_dffe.v:40: $finish called at 120 (1ns) Test tb_dffsr FST info: dumpfile tb_dffsr.fst opened for output. tb/tb_dffsr.v:67: $finish called at 250 (1ns) Test tb_dlatch FST info: dumpfile tb_dlatch.fst opened for output. tb/tb_dlatch.v:48: $finish called at 160 (1ns) Test tb_dlatchsr FST info: dumpfile tb_dlatchsr.fst opened for output. tb/tb_dlatchsr.v:63: $finish called at 250 (1ns) Test tb_sdff FST info: dumpfile tb_sdff.fst opened for output. tb/tb_sdff.v:46: $finish called at 150 (1ns) Test tb_sdffce FST info: dumpfile tb_sdffce.fst opened for output. tb/tb_sdffce.v:77: $finish called at 300 (1ns) Test tb_sdffe FST info: dumpfile tb_sdffe.fst opened for output. tb/tb_sdffe.v:68: $finish called at 250 (1ns) make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/sim' Warning: Async reset value `\ad' is not constant! Warning: Async reset value `\ad' is not constant! Warning: Complex async reset for dff `\q'. Passed sim_adlatch.ys Passed sim_dff.ys Passed sim_adff.ys Passed sim_dffe.ys Passed sim_adffe.ys Passed sim_aldff.ys Passed sim_dlatchsr.ys Passed sim_aldffe.ys Passed sim_dlatch.ys Passed sim_sdff.ys Passed sim_dffsr.ys Passed sim_sdffe.ys Passed sim_sdffce.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/sim' cd tests/svinterfaces && bash run-test.sh "" Test: svinterface1 -> svinterface1_tb.v:50: $finish called at 420000 (10ps) svinterface1_tb.v:50: $finish called at 420000 (10ps) ok Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) ERROR! Test: load_and_derive ->ok Test: resolve_types ->ok cd tests/svtypes && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/svtypes' < ok Test ../../techlibs/anlogic/cells_sim.v -> ok Test ../../techlibs/coolrunner2/cells_sim.v -> ok Test ../../techlibs/ecp5/cells_sim.v -> ok Test ../../techlibs/efinix/cells_sim.v -> ok Test ../../techlibs/gatemate/cells_sim.v -> ok Test ../../techlibs/gowin/cells_sim.v -> ok Test ../../techlibs/greenpak4/cells_sim.v -> ok Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. ok Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. ok Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. ok Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok Test ../../techlibs/intel/max10/cells_sim.v -> ok Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok Test ../../techlibs/nexus/cells_sim.v -> ok Test ../../techlibs/quicklogic/pp3/cells_sim.v -> ok Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v -> ok Test ../../techlibs/quicklogic/common/cells_sim.v -> ok Test ../../techlibs/sf2/cells_sim.v -> ok Test ../../techlibs/xilinx/cells_sim.v -> ok Test ../../techlibs/common/simcells.v -> ok Test ../../techlibs/common/simlib.v -> ok cd tests/arch/ice40 && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/arch/ice40' Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. Passed ice40_wrapcarry.ys Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. Passed ice40_dsp.ys Passed bug1626.ys Passed bug2061.ys Passed logic.ys Passed shifter.ys Passed rom.ys Passed tribuf.ys Passed add_sub.ys Passed counter.ys Passed bug1598.ys Passed mul.ys Passed ice40_opt.ys Passed bug1597.ys Passed fsm.ys Passed spram.ys Passed dffs.ys Passed latches.ys Passed macc.ys Passed mux.ys Passed adffs.ys Passed dpram.ys Passed bug1644.ys Passed memories.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/arch/ice40' cd tests/arch/xilinx && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/arch/xilinx' Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 Warning: Shift register inference not yet supported for family xc3se. Passed xilinx_srl.ys Passed xilinx_dsp.ys Passed opt_lut_ins.ys Passed bug3670.ys Warning: Wire top.\t is used but has no driver. Warning: Wire top.\in is used but has no driver. Passed xilinx_dffopt.ys Passed bug1605.ys Passed bug1462.ys Passed bug1480.ys Passed bug1460.ys Passed dsp_fastfir.ys Warning: Shift register inference not yet supported for family xc3s. Passed shifter.ys Passed counter.ys Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. Passed tribuf.ys Passed logic.ys Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. Warning: Shift register inference not yet supported for family xc3se. Passed bug1598.ys Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. Passed dsp_simd.ys /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Passed add_sub.ys Passed fsm.ys Passed mul.ys Passed pmgen_xilinx_srl.ys Passed tribuf.sh /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Passed macc.sh Passed mux_lut4.ys Passed nosrl.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. Passed mul_unsigned.ys Passed macc.ys Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. Passed latches.ys Passed dsp_abc9.ys Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. Warning: Selection "asym_ram_sdp_read_wider" did not match any module. Passed adffs.ys Passed mux.ys Passed dffs.ys Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. Passed priority_memory.ys Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. Passed attributes_test.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. Passed asym_ram_sdp.ys Warning: Shift register inference not yet supported for family xc3s. Passed lutram.ys Passed abc9_dff.ys Passed dsp_cascade.ys Passed blockram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/arch/xilinx' cd tests/arch/ecp5 && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/yosys-yosys-0.42/tests/arch/ecp5' Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' + iverilog -o iverilog-initial_display initial_display.v + ./iverilog-initial_display + diff yosys-initial_display.log iverilog-initial_display.log + test_always_display clk -DEVENT_CLK + local subtest=clk + shift + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.01s, MEM: 20.66 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 36% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: e35e8bb689, CPU: user 0.02s system 0.00s, MEM: 20.71 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 36% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v + test_always_display clk_rst -DEVENT_CLK_RST + local subtest=clk_rst + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.01s, MEM: 20.65 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 38% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: faf50513c3, CPU: user 0.02s system 0.01s, MEM: 21.23 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 35% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v + test_always_display star -DEVENT_STAR + local subtest=star + shift + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.01s, MEM: 20.94 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 37% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 8979c5de0b, CPU: user 0.02s system 0.00s, MEM: 21.35 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 35% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... + diff yosys-always_display-star-1.v yosys-always_display-star-2.v + test_always_display clk_en -DEVENT_CLK -DCOND_EN + local subtest=clk_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 1/1: $display$always_display.v:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0aec3b0a7b, CPU: user 0.01s system 0.01s, MEM: 20.77 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 39% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: df86e75db7, CPU: user 0.02s system 0.00s, MEM: 21.25 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN + local subtest=clk_rst_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 1/1: $display$always_display.v:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 07a8b6349f, CPU: user 0.01s system 0.01s, MEM: 21.49 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 39% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: fb31c18a74, CPU: user 0.01s system 0.01s, MEM: 20.60 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 39% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v + test_always_display star_en -DEVENT_STAR -DCOND_EN + local subtest=star_en + shift + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 1/1: $display$always_display.v:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: f18faacc40, CPU: user 0.02s system 0.01s, MEM: 21.04 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 39% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: e3b2b7750f, CPU: user 0.01s system 0.01s, MEM: 21.05 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 39% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= + local subtest=dec_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bfb187b86d, CPU: user 0.02s system 0.00s, MEM: 20.63 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 4be9539e85, CPU: user 0.02s system 0.00s, MEM: 21.37 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned-1 + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned-1 + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed + local subtest=dec_signed + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.01s, MEM: 20.69 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.01s, MEM: 21.31 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed-1 + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed-1 + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= + local subtest=hex_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 2377f2e106, CPU: user 0.02s system 0.00s, MEM: 21.00 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.01s, MEM: 21.23 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed + local subtest=hex_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 824c3b1e65, CPU: user 0.02s system 0.00s, MEM: 21.18 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.01s, MEM: 20.76 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= + local subtest=oct_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.01s, MEM: 20.86 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.01s, MEM: 21.36 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned-1 + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed + local subtest=oct_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7ec82b15e3, CPU: user 0.02s system 0.00s, MEM: 21.08 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: a747b9bd4f, CPU: user 0.02s system 0.00s, MEM: 20.78 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed-1 + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= + local subtest=bin_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 270b564880, CPU: user 0.02s system 0.00s, MEM: 20.55 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.01s, MEM: 21.08 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned-1 + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed + local subtest=bin_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7709253822, CPU: user 0.02s system 0.00s, MEM: 21.20 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7e2d8271c4, CPU: user 0.02s system 0.00s, MEM: 21.19 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed-1 + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log + test_cxxrtl always_full + local subtest=always_full + shift + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1. Executing Verilog-2005 frontend: always_full.v Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. Removed 0 unused cells and 207 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: always_full Automatically selected always_full as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \always_full 3.1.3. Analyzing design hierarchy.. Top module: \always_full Removed 0 unused modules. Module always_full directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. End of script. Logfile hash: 74450e80dc, CPU: user 0.03s system 0.01s, MEM: 21.88 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 28% 2x read_verilog (0 sec), 21% 2x write_cxxrtl (0 sec), ... + gcc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++ In file included from /usr/include/c++/13.2.1/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-always_full.cc:1, from always_full_tb.cc:1: /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::__enable_if_t::value_type>::value> std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_range_unique(_InputIterator, _InputIterator) [with _InputIterator = const std::pair, cxxrtl::metadata>*; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:1104:30: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 1104 | _M_insert_unique_(end(), *__first, __an); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::iterator std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_unique_(const_iterator, _Arg&&, _NodeGen&) [with _Arg = const std::pair, cxxrtl::metadata>&; _NodeGen = std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::_Alloc_node; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2271:7: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2271 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::pair std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_get_insert_hint_unique_pos(const_iterator, const key_type&) [with _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2210:5: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2210 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ./yosys-always_full + iverilog -o iverilog-always_full always_full.v always_full_tb.v + ./iverilog-always_full + grep -v '\$finish called' + diff iverilog-always_full.log yosys-always_full.log + test_cxxrtl always_comb + local subtest=always_comb + shift + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1. Executing Verilog-2005 frontend: always_comb.v Parsing Verilog input from `always_comb.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\sub'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$always_comb.v:3$13'. Set init value: \b = 1'0 Found init rule in `\top.$proc$always_comb.v:2$12'. Set init value: \a = 1'0 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1/1: $display$always_comb.v:23$19_EN Creating decoders for process `\top.$proc$always_comb.v:3$13'. Creating decoders for process `\top.$proc$always_comb.v:2$12'. Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$22' with positive edge clock. Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$23' with positive edge clock. 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. Removing empty process `sub.$proc$always_comb.v:23$15'. Removing empty process `top.$proc$always_comb.v:3$13'. Removing empty process `top.$proc$always_comb.v:2$12'. Removing empty process `top.$proc$always_comb.v:8$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module sub. Optimizing module top. Removed 0 unused cells and 7 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: sub root of 1 design levels: top Automatically selected top as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \top Used module: \sub 3.1.3. Analyzing design hierarchy.. Top module: \top Used module: \sub Removed 0 unused modules. Module sub directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). Deleting now unused module sub. 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: 0ecf9214ce, CPU: user 0.01s system 0.01s, MEM: 21.27 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 29% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + gcc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++ In file included from /usr/include/c++/13.2.1/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-always_comb.cc:1, from always_comb_tb.cc:1: /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::__enable_if_t::value_type>::value> std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_range_unique(_InputIterator, _InputIterator) [with _InputIterator = const std::pair, cxxrtl::metadata>*; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:1104:30: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 1104 | _M_insert_unique_(end(), *__first, __an); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::iterator std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_unique_(const_iterator, _Arg&&, _NodeGen&) [with _Arg = const std::pair, cxxrtl::metadata>&; _NodeGen = std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::_Alloc_node; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2271:7: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2271 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::pair std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_get_insert_hint_unique_pos(const_iterator, const key_type&) [with _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2210:5: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2210 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ./yosys-always_comb + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v + ./iverilog-always_comb + grep -v '\$finish called' + diff iverilog-always_comb.log yosys-always_comb.log + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog always_full.v; prep; clean' -- 1. Executing Verilog-2005 frontend: always_full.v Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PREP pass. 2.1. Executing HIERARCHY pass (managing design hierarchy). Module always_full directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing PROC pass (convert processes to netlists). 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.2.4. Executing PROC_INIT pass (extract init attributes). 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.3. Executing FUTURE pass. 2.4. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. Removed 0 unused cells and 207 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \always_full.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \always_full. Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.7.7. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.8. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.11.4. Finished fast OPT passes. 2.12. Printing statistics. === always_full === Number of wires: 1 Number of wire bits: 1 Number of public wires: 1 Number of public wire bits: 1 Number of ports: 1 Number of port bits: 1 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 207 $print 207 2.13. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\always_full'. End of script. Logfile hash: 55fdd6321d, CPU: user 0.05s system 0.01s, MEM: 22.58 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 24% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v + ./iverilog-always_full-1 + grep -v '\$finish called' + diff iverilog-always_full.log iverilog-always_full-1.log + ../../yosys -p 'read_verilog display_lm.v' + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1. Executing Verilog-2005 frontend: display_lm.v Parsing Verilog input from `display_lm.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\mid'. Generating RTLIL representation for module `\bot'. %l: \bot %m: \bot Successfully finished Verilog frontend. 2. Executing CXXRTL backend. 2.1. Executing HIERARCHY pass (managing design hierarchy). 2.1.1. Finding top of design hierarchy.. root of 0 design levels: bot root of 1 design levels: mid root of 2 design levels: top Automatically selected top as design top module. 2.1.2. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot 2.1.3. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot Removed 0 unused modules. Module bot directly or indirectly displays text -> setting "keep" attribute. Module mid directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing FLATTEN pass (flatten design). Deleting now unused module bot. Deleting now unused module mid. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 2 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. Cleaned up 0 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: 2cd70d7658, CPU: user 0.02s system 0.00s, MEM: 20.91 MB peak Yosys 0.42 (git sha1 9b6afcf3f83, g++ 13.2.1_git20240309 -O3 -DNDEBUG -fstack-clash-protection -fPIC) Time spent: 34% 1x opt_expr (0 sec), 16% 2x read_verilog (0 sec), ... + gcc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ In file included from /usr/include/c++/13.2.1/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-display_lm.cc:1, from display_lm_tb.cc:1: /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::__enable_if_t::value_type>::value> std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_range_unique(_InputIterator, _InputIterator) [with _InputIterator = const std::pair, cxxrtl::metadata>*; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:1104:30: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 1104 | _M_insert_unique_(end(), *__first, __an); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::iterator std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_unique_(const_iterator, _Arg&&, _NodeGen&) [with _Arg = const std::pair, cxxrtl::metadata>&; _NodeGen = std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::_Alloc_node; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2271:7: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2271 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/13.2.1/bits/stl_tree.h: In member function 'std::pair std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_get_insert_hint_unique_pos(const_iterator, const key_type&) [with _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/13.2.1/bits/stl_tree.h:2210:5: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2210 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ./yosys-display_lm_cc + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm.log %l: \bot + grep '^%m: \\bot$' yosys-display_lm.log %m: \bot + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm_cc.log %l: \bot %l: \bot + grep '^%m: \\bot$' yosys-display_lm_cc.log %m: \bot %m: \bot Passed "make test". >>> yosys: Entering fakeroot... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys strip /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys-filterlib mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys cp -r share/. /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys/. mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/ strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/libyosys.so mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so cp misc/__init__.py /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/ '/home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so' -> '/usr/lib/yosys/libyosys.so' >>> yosys-dev*: Running split function dev... >>> yosys-dev*: Preparing subpackage yosys-dev... >>> yosys-dev*: Stripping binaries >>> yosys-dev*: Running postcheck for yosys-dev >>> py3-yosys*: Running split function py3... '/home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12' -> '/home/buildozer/aports/testing/yosys/pkg/py3-yosys/usr/lib/python3.12' >>> py3-yosys*: Preparing subpackage py3-yosys... >>> py3-yosys*: Running postcheck for py3-yosys >>> yosys*: Running postcheck for yosys >>> yosys*: Preparing package yosys... >>> yosys*: Stripping binaries >>> py3-yosys*: Scanning shared objects >>> yosys-dev*: Scanning shared objects >>> yosys*: Scanning shared objects >>> py3-yosys*: Tracing dependencies... python3 yosys=0.42-r0 python3~3.12 yosys=0.42-r0 >>> py3-yosys*: Package size: 28.0 KB >>> py3-yosys*: Compressing data... >>> py3-yosys*: Create checksum... >>> py3-yosys*: Create py3-yosys-0.42-r0.apk >>> yosys-dev*: Tracing dependencies... >>> yosys-dev*: Package size: 696.0 KB >>> yosys-dev*: Compressing data... >>> yosys-dev*: Create checksum... >>> yosys-dev*: Create yosys-dev-0.42-r0.apk >>> yosys*: Tracing dependencies... abc so:libboost_filesystem.so.1.84.0 so:libboost_python312.so.1.84.0 so:libc.musl-armhf.so.1 so:libffi.so.8 so:libgcc_s.so.1 so:libpython3.12.so.1.0 so:libreadline.so.8 so:libstdc++.so.6 so:libtcl8.6.so so:libz.so.1 >>> yosys*: Package size: 50.5 MB >>> yosys*: Compressing data... >>> yosys*: Create checksum... >>> yosys*: Create yosys-0.42-r0.apk >>> yosys: Build complete at Wed, 19 Jun 2024 15:28:05 +0000 elapsed time 0h 12m 39s >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Uninstalling dependencies... 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(220/337) Purging abseil-cpp-low-level-hash (20230802.1-r0) (221/337) Purging abseil-cpp-random-internal-platform (20230802.1-r0) (222/337) Purging abseil-cpp-strings-internal (20230802.1-r0) (223/337) Purging abseil-cpp-raw-logging-internal (20230802.1-r0) (224/337) Purging abseil-cpp-spinlock-wait (20230802.1-r0) (225/337) Purging abseil-cpp-stacktrace (20230802.1-r0) (226/337) Purging abseil-cpp-strerror (20230802.1-r0) (227/337) Purging abseil-cpp-symbolize (20230802.1-r0) (228/337) Purging abseil-cpp-throw-delegate (20230802.1-r0) (229/337) Purging abseil-cpp-time-zone (20230802.1-r0) (230/337) Purging aom-libs (3.9.1-r0) (231/337) Purging boost1.84-filesystem (1.84.0-r1) (232/337) Purging graphite2-dev (1.3.14-r6) (233/337) Purging graphite2 (1.3.14-r6) (234/337) Purging cairo-dev (1.18.0-r0) (235/337) Purging cairo-tools (1.18.0-r0) (236/337) Purging xcb-util-dev (0.4.1-r3) (237/337) Purging util-macros (1.20.0-r0) (238/337) Purging xcb-util (0.4.1-r3) (239/337) Purging cairo-gobject (1.18.0-r0) (240/337) Purging cairo (1.18.0-r0) (241/337) Purging fontconfig-dev (2.15.0-r1) (242/337) Purging fontconfig (2.15.0-r1) (243/337) Purging freetype-dev (2.13.2-r0) (244/337) Purging freetype (2.13.2-r0) (245/337) Purging brotli-dev (1.1.0-r2) (246/337) Purging brotli (1.1.0-r2) (247/337) Purging glib-dev (2.80.3-r0) (248/337) Purging bzip2-dev (1.0.8-r6) (249/337) Purging docbook-xsl (1.79.2-r9) Executing docbook-xsl-1.79.2-r9.pre-deinstall (250/337) Purging docbook-xml (4.5-r9) Executing docbook-xml-4.5-r9.pre-deinstall (251/337) Purging gettext-dev (0.22.5-r0) (252/337) Purging xz (5.6.2-r0) (253/337) Purging gettext-asprintf (0.22.5-r0) (254/337) Purging gettext (0.22.5-r0) (255/337) Purging gettext-envsubst (0.22.5-r0) (256/337) Purging libxml2-utils (2.12.7-r0) (257/337) Purging libxslt (1.1.39-r1) (258/337) Purging py3-packaging (24.1-r0) (259/337) Purging py3-parsing (3.1.2-r1) (260/337) Purging pcre2-dev (10.43-r0) (261/337) Purging libpcre2-16 (10.43-r0) (262/337) Purging libpcre2-32 (10.43-r0) (263/337) Purging libedit-dev (20240517.3.1-r0) (264/337) Purging ncurses-dev (6.4_p20240420-r0) (265/337) Purging libncurses++ (6.4_p20240420-r0) (266/337) Purging bsd-compat-headers (0.7.2-r6) (267/337) Purging expat-dev (2.6.2-r0) (268/337) Purging expat (2.6.2-r0) (269/337) Purging libxrender-dev (0.9.11-r5) (270/337) Purging libxrender (0.9.11-r5) (271/337) Purging libxext-dev (1.3.6-r2) (272/337) Purging libxext (1.3.6-r2) (273/337) Purging libx11-dev (1.8.9-r1) (274/337) Purging xtrans (1.5.0-r0) (275/337) Purging libx11 (1.8.9-r1) (276/337) Purging libxcb-dev (1.16.1-r0) (277/337) Purging libxcb (1.16.1-r0) (278/337) Purging xcb-proto (1.16.0-r1) (279/337) Purging python3 (3.12.3-r1) (280/337) Purging gdbm (1.23-r1) (281/337) Purging gettext-libs (0.22.5-r0) (282/337) Purging glib (2.80.3-r0) (283/337) Purging icu (74.2-r0) (284/337) Purging icu-libs (74.2-r0) (285/337) Purging icu-data-en (74.2-r0) (286/337) Purging util-linux-dev (2.40.1-r1) (287/337) Purging libfdisk (2.40.1-r1) (288/337) Purging libmount (2.40.1-r1) (289/337) Purging libsmartcols (2.40.1-r1) (290/337) Purging util-linux (2.40.1-r1) (291/337) Purging libblkid (2.40.1-r1) (292/337) Purging libxdmcp-dev (1.1.5-r1) (293/337) Purging libxdmcp (1.1.5-r1) (294/337) Purging libbsd (0.12.2-r0) (295/337) Purging libbz2 (1.0.8-r6) (296/337) Purging libcap-ng (0.8.5-r0) (297/337) Purging libeconf (0.6.3-r0) (298/337) Purging libffi-dev (3.4.6-r0) (299/337) Purging linux-headers (6.6-r0) (300/337) Purging libffi (3.4.6-r0) (301/337) Purging libformw (6.4_p20240420-r0) (302/337) Purging libgcrypt (1.10.3-r0) (303/337) Purging libgpg-error (1.49-r0) (304/337) Purging libsm (1.2.4-r4) (305/337) Purging libice (1.1.1-r6) (306/337) Purging libintl (0.22.5-r0) (307/337) Purging libjpeg-turbo-dev (3.0.3-r0) (308/337) Purging libturbojpeg (3.0.3-r0) (309/337) Purging libjpeg-turbo (3.0.3-r0) (310/337) Purging libmd (1.1.0-r0) (311/337) Purging libmenuw (6.4_p20240420-r0) (312/337) Purging libpanelw (6.4_p20240420-r0) (313/337) Purging libpng-dev (1.6.43-r0) (314/337) Purging libpng (1.6.43-r0) (315/337) Purging libwebp-dev (1.3.2-r0) (316/337) Purging libwebpdecoder (1.3.2-r0) (317/337) Purging libwebpdemux (1.3.2-r0) (318/337) Purging libwebpmux (1.3.2-r0) (319/337) Purging libwebp (1.3.2-r0) (320/337) Purging libsharpyuv (1.3.2-r0) (321/337) Purging libuuid (2.40.1-r1) (322/337) Purging libxau-dev (1.0.11-r4) (323/337) Purging libxau (1.0.11-r4) (324/337) Purging libxml2 (2.12.7-r0) (325/337) Purging linux-pam (1.6.0-r0) (326/337) Purging mpdecimal (4.0.0-r0) (327/337) Purging pixman-dev (0.43.2-r0) (328/337) Purging pixman (0.43.2-r0) (329/337) Purging sqlite-dev (3.46.0-r0) (330/337) Purging sqlite-libs (3.46.0-r0) (331/337) Purging sqlite (3.46.0-r0) (332/337) Purging readline (8.2.10-r0) (333/337) Purging utmps-libs (0.1.2.2-r1) (334/337) Purging skalibs (2.14.2.0-r0) (335/337) Purging xorgproto (2024.1-r0) (336/337) Purging xz-libs (5.6.2-r0) (337/337) Purging zlib-dev (1.3.1-r1) Executing busybox-1.36.1-r31.trigger OK: 315 MiB in 103 packages >>> yosys: Updating the testing/armhf repository index... >>> yosys: Signing the index...